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This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. If you love solving complex signal integrity challenges and thrive on bridging the gap between design intent and manufacturing reality, we want to hear from you.

Visualize your future . . . We Do 
NVIDIA is the world leader in graphics processing technologies, creating innovative, industry-changing products for computing, consumer electronics, and mobile devices. NVIDIA products are transforming visually-rich applications such as video games, film production, broadcasting, industrial design, space exploration, and medical imaging. We invest in our people and our technologies, support and fund industry research around the world, and consistently deliver high-quality products. NVIDIA's culture promotes and inspires a team of world-class employees to be at the top of their game. We've created an environment where talents are recognized and collaboration is valued. Our employees are shaping the world of tomorrow. . . today. We invite you to explore the opportunities available at NVIDIA to see what your future may hold.

Nvidia

Signal Integrity And PCB Design Engineer

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Timing & Power Closure: Perform multi-corner multi-mode (MCMM) static timing analysis (STA), signal integrity (SI) optimization, and power grid optimization (static/dynamic IR-drop, EM) for signoff using PrimeTime, Voltus, or RedHawk. Record-Breaking Scale & Complexity: We regularly execute full-chip physical implementation for ultra-large-scale ASICs exceeding tens of billions of transistors, multi-gigahertz clock frequencies, and dense multi-die 2.5D/3D integration (CoWoS, HBM3/4, chiplet architectures).

Broadcom Corporation

Principal Physical Design Engineer

and/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing, vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training. Required for Certain Job Profiles: Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10,001 lbs.

Blue Origin

Senior Modem SOC Design Engineer - TeraWave

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Our work opens up new universes to explore, enables amazing creativity and discovery and powers what were once science fiction inventions from artificial intelligence to autonomous cars. Widely considered to be one of the technology world’s most desirable employers, NVIDIA is an industry leader with groundbreaking developments in High-Performance Computing, Artificial Intelligence and Visualization.

NVIDIA

Lead Hardware Design Validation Engineer - Memory Subsystem

Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.

Asic Design Engineer - Clocks IP

Signal Integrity and PCB Design Engineer

RESPONSIBILITIES: Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts. Job Description: Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs.

Package Design Engineer

Timing & Power Closure: Perform multi-corner multi-mode (MCMM) static timing analysis (STA), signal integrity (SI) optimization, and power grid optimization (static/dynamic IR-drop, EM) for signoff using PrimeTime, Voltus, or RedHawk. We partner with the world's most innovative technology companies-spanning hyper-scale cloud providers, AI pioneers, and tier-1 networking infrastructure leaders-to co-design and manufacture complex, custom ASICs that power the modern digital backbone.

Senior Physical Design Engineer

This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC from early architecture development phase through physical design phase, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. From the early chip definition phase you will partner closely with a wide variety of multi-disciplinary teams starting including product managers, chip architects, ASIC design, physical design, packaging teams among others to craft the chip floorplan that optimizes cost/area, performance, and power for a target market.

Senior ASIC Floorplan Design Engineer

This position involves working with the latest technology to continue driving next generation AI/ML ecosystems through our PCIe Switch Products - and managing mega datacenters, while leading world class performance, through our Enterprise Storage Products. As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.

Physical Design Engineer

Senior Asic Design Engineer - Clocks IP

YEAR

Principal Modem SOC Design Engineer - Terawave

RTL Design: Author, optimize, and maintain high-quality, synthesizable SystemVerilog/Verilog RTL for complex digital blocks, control logic, clocking structures, and register files (CSRs). Front-End Flows: Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis (STA via PrimeTime/Tempus), and run static quality checks (Lint, SpyGlass, JasperGold CDC).

Lead Asic Design Engineer

Demonstrated experience applying AI/ML techniques in engineering workflows — this could include using LLMs for code generation and debugging, building ML-assisted design analysis tools, or integrating AI-assisted flows into EDA environments. Interposers are one of the most technically demanding layers in advanced semiconductor packaging — a silicon bridge connecting multiple dies with thousands of micro-bumps, routing signals at densities that push the limits of current EDA.

Senior Physical Design Interposer Engineer

What you'll be doing: As a member of the GPU Design Methodology team, you will document and deliver design guidelines that will help the ASIC team implement high performance, area and power efficient RTL to achieve design targets and specifications. This position offers the opportunity to have a real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Senior Asic Design Engineer - Agentic AI

This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC from early architecture development phase through physical design phase, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What you will be doing: From the early chip definition phase you will partner closely with a wide variety of multi-disciplinary teams starting including product managers, chip architects, ASIC design, physical design, packaging teams among others to craft the chip floorplan that optimizes cost/area, performance, and power for a target market.

Senior Asic Floorplan Design Engineer

Broadcom Inc

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For candidates who receive an offer at the posted level, the starting base salary (for non-sales roles) or base salary + commission target (for sales/com-missioned roles) is expected to be the annual range listed below. Partner with physical-design teams: review synthesis/timing reports, rewrite RTL to close critical paths, and consult on floor-planning for congestion/routability.

Palo Alto Networks Inc

Senior ASIC Design Engineer

This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What you will be doing: Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.

Circuit Design Engineer Jobs in Milpitas, CA

Signal Integrity And PCB Design Engineer Nvidia

Principal Physical Design Engineer Broadcom Corporation

Senior Modem SOC Design Engineer - TeraWave Blue Origin

Lead Hardware Design Validation Engineer - Memory Subsystem NVIDIA

Asic Design Engineer - Clocks IP Nvidia

Signal Integrity and PCB Design Engineer NVIDIA

Package Design Engineer Broadcom Corporation

Senior Physical Design Engineer Broadcom Corporation

Senior ASIC Floorplan Design Engineer NVIDIA

Physical Design Engineer Broadcom Corporation

Senior Asic Design Engineer - Clocks IP Nvidia

Principal Modem SOC Design Engineer - Terawave Blue Origin

Lead Asic Design Engineer Broadcom Corporation

Senior Physical Design Interposer Engineer NVIDIA

Senior Asic Design Engineer - Agentic AI Nvidia

Senior Asic Floorplan Design Engineer Nvidia

Physical Design Engineer Broadcom Inc

Senior ASIC Design Engineer Palo Alto Networks Inc

Asic Floorplan Design Engineer - New College Grad 2026 Nvidia

Senior ASIC Design Engineer - Clocks IP NVIDIA Corp

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