div>Our compensation reflects the cost of labor across several U.S. geographic markets, and we pay differently based on those defined markets.
- BS in Electrical Engineering or a related field plus minimum 4 years of industry experience in analog and/or mixed-signal circuit design (or MS plus minimum 2 years of industry experience).
Santa Clara, CA14 days ago
p>What we need to see: BSEE (or equivalent experience)/MS or PhD degree preferred in Electrical or Computer Engineering with 6+ years of experience with modeling and simulation digital and analog circuits and systems and associated power delivery networks. If you are looking for a significant and exciting role in improving the netlist and timing quality of our designs and if you are a strong self-starter and highly motivated individual who loves to collaborate and find solutions to hard technical problems, join us today!
Santa Clara, CA30+ days ago
If you are looking for a challenging and exciting role in improving the netlist and timing quality of our designs and if you are a self-starter and highly motivated individual who loves to collaborate and find solutions to hard technical problems, join us today! Drive the design and physical implementation of digital and/or mixed-signal analog circuit IPs for current and voltage sensing, and common Security attacks detection and protection using custom and automated tools.
Santa Clara, CA30+ days ago
If you are looking for a significant and exciting role in improving the netlist and timing quality of our designs and if you are a strong self-starter and highly motivated individual who loves to collaborate and find solutions to hard technical problems, join us today! We are now looking for a motivated Circuit Design Engineer in Power Modeling and Simulation to join our dynamic and growing Circuits Solutions Group.
Santa Clara, CA30+ days ago
If you are interested in a challenging and exciting role to improve the power delivery of our designs, loves to collaborate and find solutions to hard technical problems, join us today! Widely considered to be one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package.
Santa Clara, CA30+ days ago
If you are looking for a challenging and exciting role in improving the netlist and timing quality of our designs and if you are a self-starter and highly motivated individual who loves to collaborate and find solutions to hard technical problems, join us today! • Drive the design and physical implementation of digital and/or mixed-signal analog circuit IPs for current and voltage sensing, and common Security attacks detection and protection using custom and automated tools.
p>Pay Rate: The annual base salary range for this position in California, Massachusetts, and New York (excluding most major metropolitan areas), Colorado, Hawaii, Illinois, Maryland, Minnesota, New Jersey, Vermont, Washington or Washington DC is $97,100 - $171,235. This is an Avionics Circuit Design Engineer role where you will work on the development, integration, and production of a sophisticated state-of the-art electronics product in a world class Integrated Product Development environment.
Santa Clara, CA4 days ago
p>Business group: The Central Engineering Group (CEG) is Intel''s data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies).
Qualifications:
Minimum Qualifications - Bachelor''s degree in Electrical Engineering, Computer Engineering, or a related field, with 3+ years of relevant experience, or a Master''s degree with 2+ years of experience, or a PhD with no prior experience.
Sunnyvale, California30+ days ago
p style="min-height:1.5em">Taara is seeking a Senior Photonic Circuits Design Engineer to work on next-generation photonic and electronic integrated modules as part of the R&D team developing cutting-edge wireless optical communication systems based on integrated optical phased arrays. The successful candidate will own photonic circuit architecture, photonic spectral filter design, and photonic switch design within the very-large-scale photonic integrated circuits (PICs) designed at Taara.
Sunnyvale, CA30+ days ago
p>The CMOS Mixed-Signal Circuit Design Engineer contributes to the development of advanced mixed signal circuits for low-power and high performance PLLs, PVT sensors and I/O's to be used in numerous products from high performance data center SoCs to low power consumer SoCs. We specialize in developing advanced mixed signal circuits for low power, high-speed, Fin-FET mixed-signal and analog IPs that are used in numerous products from high performance data center SoCs to low power consumer SoCs.
Deep knowledge of ADC/DAC architectures and knowing which are suitable for given applications Deep knowledge of band-gaps, bias, op-amps, switched-cap circuits, LDOs, feedback and compensation techniques Proven expertise in the following areas: Significant knowledge of low noise design techniques Significant knowledge of high precision techniques in presence of device mismatch Experience in C / Matlab / Verilog modeling Strong device physics knowledge as it applies to analog IC designs Proven working experience in using spectrum analyzers, oscilloscopes, signal generators, etc. to validate analog designs Extensive experience working with production test engineers to firm up test plans and design for testability details. Bachelors of Science in Electric Engineering with 10+ years of relevant experience preferredDo you have a proven track record of taking chips to production in the following areas?
p>Pay Rate: The annual base salary range for this position in California, Massachusetts, and New York (excluding most major metropolitan areas), Colorado, Hawaii, Illinois, Maryland, Minnesota, New Jersey, Vermont, Washington or Washington DC is $97,100 - $171,235. As a leading technology innovation company, Lockheed Martin's vast team works with partners around the world to bring proven performance to our customers' toughest challenges.
Santa Clara, CA30+ days ago
p>Business group: The Central Engineering Group (CEG) is Intel''s data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies).
Job Details:
Job Description:
We are seeking a highly experienced and motivated Principal Analog Design Engineer to lead the design and validation of cutting-edge analog circuits for high-speed (112G and 224G) SerDes applications.
San Jose, California4 days ago
p style="text-align:inherit"/>The Non-Volatile Engineering (NVEG) NAND Flash design and verification team at Micron Technology develops advanced memory solutions that deliver leading die size, performance, reliability, and power efficiency. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on
micron.com/careers/benefits.
Enabling the movement towards advanced chip design, KLA''s Global Products Group (GPG), which is responsible for creating all of KLA's metrology and inspection products, is looking for the best and the brightest research scientist, software engineers, application development engineers, and senior product technology process engineers. These tasks will require working with other engineering groups such as Mechanical, Optical, Software, Systems and Manufacturing engineering teams, ensuring design, integration and qualification at subsystem and system levels.
Santa Clara, CA3 days ago
p>You will be partnering with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel advanced CMOS process technologies. Business group:
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly.
ul>Bachelor's degree in electrical engineering with 20+ years of industry experience or master's degree in electrical engineering with 18+ years of experience strongly preferred. Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.
Cupertino, CA30+ days ago
p>You will work on the development of high-performance and high-speed AMS circuits used in SerDes PHY, including evaluation of different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO) with best-in-class power, performance, and area (PPA). Experience of designing analog mixed signal circuit blocks including Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, switched-cap circuits, ADCs, DACs, Oscillators, Filters.
From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Collaborate closely with signal integrity/power integrity (SI/PI), thermal, and mechanical engineering teams to refine and optimize product package designs, test vehicles, and mock-up designs for product feasibility.
Santa Clara, CA30+ days ago
Apply transistor level integrated circuits analog IP requirements and architecture principles to study module circuit specifications. Complete layout design, conduct full-chip simulation verification, and perform layout problem analysis and positioning.
em> Expertise in analog/digital simulator (HSPICE, Verilog, XA, Finesim) Expertise in scripting language (Perl, Python, C++) Familiarity with Cadence design, LVS/SRC tools The US base salary range that Micron Technology estimates it could pay for this full-time position is: $116,000.00 - $246,000.00 a year Additional compensation may include benefits, bonuses and equity. Proactively design and verify products to optimize all manufacturing function and provide the best cost, quality, root-cause analysis, reliability, time-to-market, and customer satisfaction Minimum Qualification: 7+ years on transistor level Analog and digital logic IC design experience using CMOS!
Redwood City, California30+ days ago
ITAR Requirements: - To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.
- Hands-on experience laying out high-performance platforms including compute (SoCs, FPGAs, MCUs), storage (DDR, SSDs), high-speed interfaces (PCIe, SPI, JESD204B), RF components (PAs, LNAs, switches).
Sunnyvale, CA30+ days ago
p>In this role, the engineer will work closely with other members of the Analog and Digital Design groups, and other functions such as Clinical, Electrical Systems Engineering, Firmware Development, ATE, and Manufacturing. Our portfolio of life-changing technologies spans the spectrum of healthcare, with leading businesses and products in diagnostics, medical devices, nutritionals and branded generic medicines.
Sunnyvale, California30+ days ago
United States > Minneapolis : 800 Nicollet Mall, United States > Scottsdale : 8300 E. Pacesetter Way, United States > Sylmar : 15900 Valley View Court, United States > Texas > Plano : 6901 Preston Road . Continuous sitting for prolonged periods (more than 2 consecutive hours in an 8 hour day), Keyboard use (greater or equal to 50% of the workday)
.
p>Design next-generation RF integrated circuits that enable ultra-high-speed interconnects for modern data centers. Work on cutting-edge mmWave and sub-THz ICs and contribute directly to Point2's core product architecture.
Santa Clara, CA30+ days ago
p>Ways to stand out from the crowd: • Experience with ML/DL algorithms with frameworks such as TensorFlow, PyTorch, Spark is a plus • Working with multiple levels and teams across organizations (engineering/research, product, sales and marketing teams) • Prior experience in CMOS layout drawing, including schematic-to-layout translation and DRC/LVS compliance, is a definite plus • Effective verbal/written communication, and technical presentation skills • Proven continuous learning and sharing findings across the team. • Responsible for translating the requirements into a data science problem, architect and build solutions • In charge for testing and release of models that integrate with existing machine learning and visualization tools within the organization • Responsible for analyzing the datasets, raise and validate hypotheses, extract relevant features and build models on top of them • Optimize the models and algorithms until they reach the desired QOR.
p>Job Responsibility: Analog / SERDES Circuit Design · Architect, design, and simulate analog circuit blocks that comprise the AFE, including: o Transmit (TX) circuits: line drivers, pre‑drivers, output stages o Receive (RX) circuits: front‑end amplifiers, CTLE, PGA, slicers o Clocking circuits: PLLs, DLLs, clock distribution, jitter filtering · Translate system‑ and PHY‑level requirements into robust block‑level specifications.
Examples of Core Technical Expertise · High‑speed TX and RX circuit design · Linearity, distortion, and noise analysis · Jitter generation, tolerance, and clock integrity · PLL / DLL and clocking architectures · PVT variation and automotive robustness · Advanced CMOS processes for high‑speed analog.
From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving channel behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Through comprehensive and robust analysis of large, ever-expanding datasets obtained from existing quantum processors and test devices, you will extract relevant empirical calibrations to improve the accuracy of our processor design and the performance of subsequent generations of processors. Utilize techniques and best practices in statistical analysis and machine learning to accurately calibrate various processor design parameters, leveraging the large datasets generated from measurements on our quantum processors and dedicated monitoring devices.
li>Knowledge of all facets of high speed I/O design but specifically should include DLL / PLL / FFE / CTLE / DFE, output drivers , ODT, Duty cycle correction (DCC), Training/calibration to improve timing, high speed power design and low power design. 5+ years of experience working with system on chip architecture, high-speed serial interfaces, and analog mixed-signal circuit design using advanced CMOS technology nodes.
Santa Clara, CA30+ days ago
This role will develop new tools, improve and maintain existing ones, and promote their use across various departments to achieve rapid tapeout schedules, better design quality, and efficient AI integration within our flows! What you'll be doing:
We need someone who will architect, develop, and collaborate with our software development teams to implement new in-house tools that support mixed-signal project, cell specification, and circuit deliverable tracking.
Santa Clara, CA30+ days ago
The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.
You will be directly responsible for the full life-cycle of tool development including data storage design, UI design, testing, development, deployment, and maintenance.
Santa Clara, CA30+ days ago
D. degree or Masters +3 years of experience in optical engineering, physics, and electrical engineering Prior experience with solid-state physics, integrated photonics, and opto-electronics Prior experience with high speed electronic and photonic components testing more than 60GHz Prior experience with RF and photonics numerical simulation principle and tools, such as FDTD, ADS, HFSS, COMSOL, Cadence, etc. Prior experience with script-based photonic component GDS layout and tapeout, especially experience with commercial silicon photonics foundries Prior experience with demonstrated integrated optoelectronic device and circuit design and fabrication.
Pay Rate: The annual base salary range for this position in California, Massachusetts, and New York (excluding most major metropolitan areas), Colorado, Hawaii, Illinois, Maryland, Minnesota, New Jersey, Vermont, Washington or Washington DC is $139,600 - $246,100. As an Electronics Engineer for the central circuit design group, you will join a team of subject matter experts for Worst Case Circuit Analysis (WCCA), responding to the enterprise needs of our programs as they work through their development phase.
Applied Mathematics (any of the following is a plus) Optimization: linear, nonlinear, convex, integer, stochastic, variational; robust/multi-objective; derivative-free/global methods (e.g., CMA-ES, Bayesian optimization). Rare-event and reliability analysis (a plus): importance sampling, subset simulation, cross-entropy methods, extreme value/tail modeling, yield estimation.
Santa Clara, CA30+ days ago
p>Minimum Qualifications: MS degree in Electrical Engineering, Physics, or a similar discipline with 5+ years of experience in a related field with years of relevant industry experience in the required skills section below OR PhD Electrical Engineering, Physics, or a similar discipline and 3+ years of experience in a related field with years of relevant industry experience in the required skills section below. • Experience designing, simulating, and testing complex PICs, including link budget analysis, electrical power budgets, back-reflection budgets, Monte Carlo models, and other performance indicators.