R&D Engineer IC Design Broadcom CorporationR&D Engineer IC DesignSan Jose, CA$120,000–$192,000 / yearStrong automation expertise related to bump pattern generation, routing structure development for high speed interfaces, and chip finishing are required to handle multiple Interposer designs in parallel. You will be working on designing interposers starting with custom routing for high speed interfaces, bump map design, routing and physical verification and tapeout to the foundries.
Senior Asic Design Verification Infrastructure And Tools Engineer - GPU NvidiaSenior Asic Design Verification Infrastructure And Tools Engineer - GPUSanta Clara, CAThis position offers the opportunity to have a big impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to artificial intelligence to self-driving cars and supercomputers. NVIDIA is seeking outstanding Senior Design Verification Engineers with a specialty in tools and automation to drive efficiency and collaboration among our High Speed IO engineering teams.
Physical IC Design Engineer Broadcom CorporationPhysical IC Design EngineerSan Jose, CAThis position involves working with the advanced nodes to continue driving next generation Artificial Intelligence and Machine Learning ecosystems through our PCIe Switch Products, while leading world class performance, through our Enterprise Products. As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.
Senior SOC Design Engineer NvidiaSenior SOC Design EngineerSanta Clara, CAAs a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software, DFT, and more. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.
Package Design Engineer Broadcom CorporationPackage Design EngineerSan Jose, CA$141,300–$226,000 / yearRESPONSIBILITIES: Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts. Job Description: Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs.
Sr. Asic Design Engineer Micron Technology, Inc.Sr. Asic Design EngineerSan Jose, CA$168,000–$336,000 / yearWhat's Encouraged Daily: As a Senior ASIC Design Engineer and domain expert, you will perform logic design across the full ASIC lifecycle from specifications and microarchitecture to design, integration, synthesis, timing, linting, and CDC. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.
Senior Physical Design Engineer NvidiaSenior Physical Design EngineerSanta Clara, CAAlready a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR-RC/ICV),Cadence (Innovus, Tempus, SeaHawk ) and Mentor Graphics. As a member of a team, we will all participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure.
IC Design Engineer Broadcom CorporationIC Design EngineerSan Jose, CAJob Description: Broadcom's ASIC Products Division is seeking a Design Automation Software Development Engineer in the Design For Test (DFT) team developing SoC ASIC products. This job will involve development, testing and deployment of software products and usage methodology to a world-wide, cutting edge, ASIC DFT technology development and implementation team.
Senior Asic Design Engineer - Agentic AI NvidiaSenior Asic Design Engineer - Agentic AISanta Clara, CAWhat you'll be doing: As a member of the GPU Design Methodology team, you will document and deliver design guidelines that will help the ASIC team implement high performance, area and power efficient RTL to achieve design targets and specifications. This position offers the opportunity to have a real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.
Lead Asic Design Engineer Broadcom CorporationLead Asic Design EngineerSan Jose, CA$143,800–$230,000 / yearRTL Design: Author, optimize, and maintain high-quality, synthesizable SystemVerilog/Verilog RTL for complex digital blocks, control logic, clocking structures, and register files (CSRs). Front-End Flows: Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis (STA via PrimeTime/Tempus), and run static quality checks (Lint, SpyGlass, JasperGold CDC).
Senior Asic Floorplan Design Engineer NvidiaSenior Asic Floorplan Design EngineerSanta Clara, CAThis position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC from early architecture development phase through physical design phase, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What you will be doing: From the early chip definition phase you will partner closely with a wide variety of multi-disciplinary teams starting including product managers, chip architects, ASIC design, physical design, packaging teams among others to craft the chip floorplan that optimizes cost/area, performance, and power for a target market.
Asic Design Engineer - New College Grad 2026 NvidiaAsic Design Engineer - New College Grad 2026Santa Clara, CAThis position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What you'll be doing: As a key member of the GPU Design team, you will implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications.
Senior Hardware System Design Engineer Broadcom CorporationSenior Hardware System Design EngineerSan Jose, CA$120,000–$192,000 / yearThe ideal candidate will play a key role in the entire hardware development cycle, from concept to NPI production, with a specific emphasis on system design, including schematics, PCB layout, signal and power integrity, system bring-up, and customer support. Join Our Team: If you are a passionate and self-driven individual with a knack for solving complex hardware design challenges, we invite you to apply and become a key member of our innovative team at Broadcom's Core Switching Group.
Staff/Principal Hardware System Design Engineer Micron Technology, Inc.Staff/Principal Hardware System Design EngineerSan Jose, CA$202,000–$344,000 / yearThis role focuses on tester hardware architecture and platform-level electrical design, integrating host compute, PCIe interfaces, high-speed interconnects, DUT interface hardware, power delivery, sideband control, firmware/software interfaces, and manufacturing needs into a complete test system. Hands-on experience with PCB schematic design/review, BOM development, component selection, board-level tradeoffs, and high-speed hardware considerations including SI/PI, thermal constraints, cost, and manufacturability.
Asic Floorplan Design Engineer - New College Grad 2026 NvidiaAsic Floorplan Design Engineer - New College Grad 2026Santa Clara, CAThis position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What you will be doing: Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.
Lead Hardware Design Validation Engineer - Memory Subsystem NvidiaLead Hardware Design Validation Engineer - Memory SubsystemSanta Clara, CAOur work opens up new universes to explore, enables amazing creativity and discovery and powers what were once science fiction inventions from artificial intelligence to autonomous cars. Widely considered to be one of the technology world's most desirable employers, NVIDIA is an industry leader with groundbreaking developments in High-Performance Computing, Artificial Intelligence and Visualization.
New(Mid/Sr/Staff/Princ) Layout Design Engineer (SerDes) Thrive Recruitment Agency(Mid/Sr/Staff/Princ) Layout Design Engineer (SerDes)Sunnyvale, CaliforniaIn this position you will play a key role in contributing to the development of advanced mixed-signal layout for low-power, high-speed, SERDES, sensors, PLL and other macros to be used in numerous products from high performance data center SOCs to low-power consumer SOCs. Tasks include planning and implementing block-level floor-planning, power distribution network, clock and signal routing, analog and mixed-signal transistor level layout.
New(Mid/Sr/Staff/Princ) Layout Design Engineer (FinFETs/5/7/12/16nm) Thrive Recruitment Agency(Mid/Sr/Staff/Princ) Layout Design Engineer (FinFETs/5/7/12/16nm)Sunnyvale, CaliforniaIn this position you will play a key role in contributing to the development of advanced mixed-signal layout for low-power, high-speed, SERDES, sensors, PLL and other macros to be used in numerous products from high performance data center SOCs to low-power consumer SOCs. Tasks include planning and implementing block-level floor-planning, power distribution network, clock and signal routing, analog and mixed-signal transistor level layout.
NewSenior Mechanical Design Engineer Blue Chip TalentSenior Mechanical Design EngineerPalo Alto, CAResponsibilitiesDesign modular and reusable mechanical fixtures for testing vehicle electronicsDevelop mechanical interfaces including pogo-pin and bed-of-nails style probingDefine mechanical test requirements in collaboration with cross-functional teamsDesign rack-based systems to streamline complexity and replication at scaleProduce detailed documentation including BOMs, drawings, and SOPsOversee vendors during mechanical system manufacturing and integrationSupport technicians during station build and commissioningEnsure robust implementation of test system requirementsQualificationsRequired:BS/MS in Mechanical Engineering or related field (or equivalent experience)5–10 years of experience designing modular mechanical hardware for test systemsProficiency in 3D CAD tools such as SolidWorks (strongly preferred), Inventor, AutoCAD, or ProEHands-on experience with electronics testing and probing technologies (e.g., VPC, Ingun)Ability to interpret electrical schematics and PCB layoutsExperience with hardware integration in automated test environmentsBackground in automotive, semiconductor, or aerospace industriesFamiliarity with automotive communication protocols (CAN, CANFD, LIN, DoIP, Automotive Ethernet)Experience deploying automated test equipment in manufacturingExposure to instrumentation such as power supplies, multiplexers, DMMs, signal analyzers, and generatorsBlue Chip Talent is an award-winning and woman-owned talent solutions provider based in Bloomfield Hills, Michigan. This role is responsible for designing modular mechanical test systems for vehicle electronics and developing hardware solutions that support testing across R&D to high-volume manufacturing environments.
NewSenior Electrical Design Engineer - Robotics PCB & Equity Matic RobotsSenior Electrical Design Engineer - Robotics PCB & EquityMenlo Park, CA$160,000–$240,000 / yearMatic Robots is seeking a Senior Electrical Design Engineer to lead the design of critical PCBs and subsystems of innovative home robotics products. The ideal candidate has a technical degree in Electrical Engineering, over 4 years of professional experience, and is passionate about building exceptional products.
NewLead Photonic Netlist & Design Automation Engineer PsiQuantumLead Photonic Netlist & Design Automation EngineerPalo Alto, CA$130,000–$145,000 / hourApplicants should possess 6+ years of relevant experience, strong Python skills, and familiarity with tools like KLayout and Cadence Virtuoso. The expected salary range is $130,000 to $145,000 USD, with a higher Bay Area range up to $165,000 USD.
NewStaff Hardware Design Engineer, Quantum Systems PsiQuantumStaff Hardware Design Engineer, Quantum SystemsMilpitas, CA$141,000–$213,000 / yearThis role focuses on owning hardware designs for quantum computers, including working with thermal, mechanical, firmware, and optical engineers. Work involves designing PCBs, ensuring signal integrity, and characterizing analog and digital circuitry.
Senior ASIC Design Engineer Ethan Alexander GroupSenior ASIC Design EngineerSan Francisco, CaliforniaFamiliarity with lab equipment including logic analyzers, oscilloscopes, and multimeters. Define and bring up FPGA platforms for pre-silicon validation and software development.
Design Verification Engineer IV Arrow Electronics IncDesign Verification Engineer IVSan Jose, CA$87,400–$132,000 / yearAlong with Arrow's $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals.
Design Verification Engineer (Einfochips Inc) Arrow Electronics Inc,Design Verification Engineer (Einfochips Inc)San Jose, CA$87,400–$132,000 / yearAlong with Arrow's $38B in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is primed to accelerate connected products innovation for 150,000+ global clients. A rich history of over two decades, with over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals.
High Speed IO Analog Mixed Signal Design Engineer Advanced Micro Devices, IncHigh Speed IO Analog Mixed Signal Design EngineerSan Jose, CaliforniaBe part of AMD’s analog/mixed signal IP design team responsible for the design and development of next generation IOs, high speed memory (LPDDRx, gDDRx, HBMx) and die-to-die Gbps proprietary PHY IP solutions. Hand-on design experience in multi-Gbps serial (PCIE, USB, …), parallel high BW memory interface PHY/IOs (DDR4/DDR5, HBM2/HBM3, gDDR5/gDDR6, …) and chip-to-chip links PHY IPs.
NewStaff High Voltage Electrical Engineer, EPC Redwood MaterialsStaff High Voltage Electrical Engineer, EPCSan Francisco, CA$190,000–$252,500 / yearStaff High Voltage Electrical Engineer, EPCRedwood Materials is seeking a Staff High Voltage Electrical Engineer to join our EPC team. Our mission is to build a sustainable circular economy for lithium-ion batteries by transforming recycled materials into high-quality inputs for new batteries.
Substation Protection And Control Engineer, EPC Redwood MaterialsSubstation Protection And Control Engineer, EPCSan Francisco, CA$190,000–$252,500 / yearResponsibilities will include: Lead the design of high voltage AC electrical systems, specifically for industrial substations (69kV to 345kV) and their integration with upstream transmission lines and downstream MV distribution. Redwood is localizing a global battery supply chain that seamlessly integrates recovery, reuse, and recycling - keeping critical minerals in circulation and driving the energy transition.
Staff High Voltage Electrical Engineer, EPC Redwood Materials IncStaff High Voltage Electrical Engineer, EPCSan Francisco, CA$190,000–$252,500 / yearResponsibilities will include: Lead the design of high voltage AC electrical systems, specifically for industrial substations (69kV to 345kV) and their integration with upstream transmission lines and downstream MV distribution. Redwood is localizing a global battery supply chain that seamlessly integrates recovery, reuse, and recycling - keeping critical minerals in circulation and driving the energy transition.
Vice President of Engineering - Optical Circuit Switch (OCS) Coherent CorpVice President of Engineering - Optical Circuit Switch (OCS)Sunnyvale, CAWe are a vertically integrated manufacturing company that develops innovative products for diversified applications in the industrial, optical communications, military, life sciences, semiconductor equipment, and consumer markets. Coherent provides a comprehensive career development platform within an environment that challenges employees to perform at their best, while rewarding excellence and hard-work through a competitive compensation program.
NewHardware Design Engineer Super Micro Computer Spain, S.L.Hardware Design EngineerSan Jose, CADate: Jun 15, 2026Location: San Jose, California, United StatesCompany: Super Micro ComputerJob Req ID: 29120About SupermicroSupermicro® is a Top Tier provider of advanced server, storage, and networking solutions for Data Center, Cloud Computing, Enterprise IT, Hadoop/ Big Data, Hyperscale, HPC and IoT/Embedded customers worldwide. You will work closely with cross-functional engineering teams and external partners to deliver robust, competitive, and high-quality board designs.
Principle Design Verification Engineer SerDes/PHY Astera Labs IncPrinciple Design Verification Engineer SerDes/PHYSan Jose, CA$207,000–$230,000 / yearYou''ll partner directly with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks that ship into the world''s most advanced AI platforms, including UALink, UCIe, PCIe Gen 6/Gen 7, and Ethernet-based connectivity products. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Timing Design Engineer Apple IncTiming Design EngineerCupertino, CAYou will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints.
Design Verification Engineer, Staff Astera Labs IncDesign Verification Engineer, StaffSan Jose, CA$160,000–$195,000 / yearUsing your expertise in SystemVerilog, UVM, and problem-solving skills, youll contribute to the functional verification of cutting-edge designs supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. Youll be responsible for the full verification lifecycle-from planning to test development to debugging and coverage closure-while collaborating with RTL designers and system validation teams.
Sr. Software Development Engineer (Applied ML)-Hardware Product Design Apple IncSr. Software Development Engineer (Applied ML)-Hardware Product DesignSunnyvale, CAYou'll join the Data Science and Visualization (DataViz) team in Hardware Engineering at Apple, working day-to-day in close partnership with Apple's Advanced Development Lab (ADL) to bring machine learning into the heart of their machining and prototyping workflows. Hands-on experience designing or extending agentic AI systems (multi-step, tool-using workflows where models plan, act, and recover) and the evaluation frameworks that keep them reliable - including ground truth that is contested, expensive, or partial, and small labeled datasets.
Technical Lead Design Verification Engineer Astera Labs IncTechnical Lead Design Verification EngineerSan Jose, CAAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Principal Design Verification Engineer Astera Labs IncPrincipal Design Verification EngineerSan Jose, CA$185,000–$230,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Technical Lead Design Verification Engineer Astera LabsTechnical Lead Design Verification EngineerSan Jose, CAAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Senior Staff PCB Layout Design Engineer D-MatrixSenior Staff PCB Layout Design EngineerSanta Clara, CAPower Delivery Optimization: Work with Power Engineers to implement complex PDN strategies, including multi-phase VRM layouts and optimized decoupling capacitor placement for high-TDP ASICs. You will own the layout of high-complexity, high-layer-count PCBAs (20+ layers), ensuring that 112G/224G SerDes signals remain pristine and that thousands of Amps are delivered across the board with minimal loss.
Principle Design Verification Engineer Serdes/Phy Astera LabsPrinciple Design Verification Engineer Serdes/PhySan Jose, CA$207,000–$230,000 / yearYou'll partner directly with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks that ship into the world's most advanced AI platforms, including UALink, UCIe, PCIe Gen 6/Gen 7, and Ethernet-based connectivity products. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
NewStaff Product Design Engineer NicedesignjobsStaff Product Design EngineerSan Francisco, CA$198,000–$233,000 / yearStaff Product Design Engineer Location: Hybrid - San Francisco, CaliforniaAbout Oura Our mission at Oura is to empower every person to own their inner potential. The company's award-winning products help users understand their readiness, activity, and sleep quality through the Oura Ring and connected app.
NewLead Hardware Design Engineer, Server Motherboards supermicroLead Hardware Design Engineer, Server MotherboardsSan Jose, CAThe role requires strong x86 hardware expertise, high-speed signal integrity, and power regulation know-how, with hands-on PCB design and debugging skills, plus leadership potential within 12 months.#J-18808-Ljbffr. Hardware Design Engineer to drive development of in-house server motherboards, collaborating with cross-functional teams and external partners to ensure robust, high-performance board designs.
NewPrincipal Design Verification Engineer Astera LabsPrincipal Design Verification EngineerSan Jose, CA$185,000–$230,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
NewLead Power & Board Design Engineer for ASICs Astera LabsLead Power & Board Design Engineer for ASICsSan Jose, CA$209,000–$230,000 / yearThis role involves designing and optimizing power systems for ASIC products, ensuring robust power integrity. Candidates should have 8-10 years of experience in power and board design engineering, and be proficient in Cadence OrCAD and Allegro.
NewSenior Principal Board Design Engineer Bright Vision TechnologiesSenior Principal Board Design EngineerSanta Clara, CAFull timeIn this customer-facing technical leadership role, you will work closely with customers and internal engineering teams to support hardware design from architecture through production, ensuring high-performance, reliable, and manufacturable solutions. As we continue to grow, we’re looking for a skilled Senior Principal Board Design Engineer to join our dynamic team and contribute to our mission of transforming business processes through technology.
FPGA Design Engineer Reliable Robotics CorporationFPGA Design EngineerMountain View, CaliforniaFPGA designers at Reliable Robotics have a unique opportunity to work within a vertically integrated technology stack that extends up to the aircraft level, with a direct impact on the aircraft's capabilities and requirements. In your role as an FPGA Design Engineer, you will work in a highly collaborative and cross-functional development environment including mutual peer review to maintain high product quality.
Physical Design Engineer EtchedPhysical Design EngineerSan Jose, Californiawill own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed. Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis.
IC Package Design Engineer CiscoIC Package Design EngineerSan Jose, CaliforniaThe applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $152,500.00 - $252,000.00 Non-Metro New York state & Washington state: $135,800.00 - $224,400.00 * For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally.
Sr. Asic Design Verification Engineer (Silicon Engineering) Space Exploration TechnologiesSr. Asic Design Verification Engineer (Silicon Engineering)Palo Alto, CA$175,000–$280,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Sr. FPGA Design Engineer Reliable Robotics CorporationSr. FPGA Design EngineerMountain View, CaliforniaFPGA designers at Reliable Robotics have a unique opportunity to work within a vertically integrated technology stack that extends up to the aircraft level, with a direct impact on the aircraft's capabilities and requirements. In your role as an FPGA Design Engineer, you will work in a highly collaborative and cross-functional development environment including mutual peer review to maintain high product quality.