SoC Power Architecture Engineer - Processor Subsystem E-SpaceSoC Power Architecture Engineer - Processor SubsystemSaratoga, CA$150,000–$220,000 / yearThis role focuses on partitioning and structuring power domains within complex processor subsystems, with a strong emphasis on the aggressive duty cycling, ultra-low standby power, and constrained energy budgets inherent to satellite IoT end-node devices. We are seeking an experienced SoC Power Architecture Engineer to define, design, and implement power domain architectures for ASIC-based processor subsystems targeting satellite IoT connectivity applications.
Principal Product Engineer - Virtual Protocols Cadence Design Systems IncPrincipal Product Engineer - Virtual ProtocolsSan Jose, CA$136,500–$253,500 / yearThis position presents exciting opportunities and challenges of becoming an expert in System Level Software Driven Verification use models that leverage advanced protocol engines operating on Cadences Palladium and Protium Emulation products to enable the critical shift-left of System Level SOC verification and Validation for Cadence customers. Their responsibilities can be but are not limited to: Using expertise in OS, kernel, and driver SW development to support Cadence VirtualBridge products that combine a Virtual Machine running a production OS with the customers SOC Design running on Cadences Palladium emulation or Protium Prototyping platforms.
Staff Systems Validation Engineer Agility Robotics IncStaff Systems Validation EngineerFremont, CA$177,000–$230,000 / yearAgility's commercially deployed humanoids operate alongside teams in warehouses, manufacturing facilities, and distribution centers-tackling physically demanding and repetitive tasks while enabling workers to focus on higher-value work. Experience validating machine learning-based software components or models, including working with software integration teams to define acceptance criteria, manage model versioning, and assess behavioral drift or regression across releases.
NewSenior EDA Tools Software Engineer Intel CorpSenior EDA Tools Software EngineerSanta Clara, CA$173,660–$330,340 / yearMinimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or a related field, with 7+ years of experience in CAD/EDA tooling, design automation, or semiconductor development OR Master's degree in Electrical Engineering, Computer Science, or a related field, with 6+ years of experience in CAD/EDA tooling, design automation, or semiconductor. Chassis refers to non-compute infrastructure in any soc, which provide essential platform services and typically include interconnects, protocol bridges, clock/reset/power, security, debug/trace/analytics (DTA), RAS error logic, address maps, firmware tables etc.
RTL Design Engineer Normal Computing CorpRTL Design EngineerPalo Alto, CAYou will own RTL from microarchitecture to tapeout: writing synthesizable SystemVerilog, authoring verification environments in UVM, cocotb, or formal tools, and working closely with architecture and physical design to make sure what you build is both functionally correct and physically realizable. This work sits at the intersection of classical ASIC design, novel computing architectures, and a development environment where the hardware and the algorithms are built together, not in sequence.
Senior Electrical Engineer Dexterity.aiSenior Electrical EngineerRedwood City, CA$135,000–$172,000 / yearCollaborate with Hardware Test engineers to develop and execute robust testing plans to verify the functionality and performance of electrical systems, analyzing test results to drive continuous improvement. Dexterity is one of the fastest-growing companies in robotics, backed by world-class investors such as Kleiner Perkins, Lightspeed Venture Partners, and Obvious Ventures.
NewDFT Engineer, Google Cloud Google LLCDFT Engineer, Google CloudSunnyvale, CAAs a DFT Engineer, you will be responsible for defining, implementing and deploying advanced design-for-test (DFT) methodologies including Scan, Memory Built-In Self-Test (MBIST), Joint Test Action Group (JTAG) and iJTAG, for highly complex digital or mixed-signal chips or IPs. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Senior Mixed Signal Design Engineer NvidiaSenior Mixed Signal Design EngineerSanta Clara, CAThis position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What we need to see: Hold a Master of Science in Electrical Engineering, Computer Engineering or related field with strong analog design background (or equivalent experience).
Senior Signaling Engineer Arup Group LtdSenior Signaling EngineerSan Francisco, CA$170,000–$190,000 / yearWe offer a broad range of services spanning planning, design, delivery, systems integration, assurance, safety and security assessments, and optimization of railway operation and maintenance performance to unlock the financial value for investors, asset owners, operators and maintainers, while navigating the transition to low carbon and resilient rail. You will be a key member of Arup's San Francisco engineering team spending significant time in our Sacramento office on the California High Speed Rail, Track and Systems contract, and you will be instrumental in developing Arup's business and capability in Signaling & Train Control in North America.
Senior Traction Power Engineer Arup Group LtdSenior Traction Power EngineerSan Francisco, CA$170,000–$190,000 / yearWe offer a broad range of services spanning planning, design, delivery, systems integration, assurance, safety and security assessments, and optimization of railway operation and maintenance performance to unlock the financial value for investors, asset owners, operators and maintainers, while navigating the transition to low carbon and resilient rail. Our internal employee networks support our inclusive culture: from race, ethnicity and cross-cultural working to gender equity and LGBTQ+ and disability inclusion - we aim to create a space for you to express yourself and make a positive difference.
Senior Wafer Test Hardware Engineer, Raxium Google LLCSenior Wafer Test Hardware Engineer, RaxiumFremont, CAGoogle"s Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field (e.g., Optics, Sensors, Audio/DSP, etc.), or equivalent practical experience.
Senior Systems Engineer, Test Frameworks & Validation Platform CoreWeave IncSenior Systems Engineer, Test Frameworks & Validation PlatformSunnyvale, CA$153,000–$204,000 / yearTo conform to U.S. Government export regulations applicable to that information, applicant must either be (A) a U.S. person, defined as a (i) U.S. citizen or national, (ii) U.S. lawful permanent resident (green card holder), (iii) refugee under 8 U.S.C. § 1157, or (iv) asylee under 8 U.S.C. § 1158, (B) eligible to access the export controlled information without a required export authorization, or (C) eligible and reasonably likely to obtain the required export authorization from the applicable U.S. government agency. We build and operate the test framework that qualifies every server image on real physical hardware before it reaches one of the largest GPU fleets in the world, and we''re extending that framework into HPC verification, Slurm-on-Kubernetes, and further down the stack.
ASIC Design Verification Technical Lead, TPU Google LLCASIC Design Verification Technical Lead, TPUSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
SoC Platform Engineer E-SpaceSoC Platform EngineerSaratoga, CA$150,000–$220,000 / yearYou will work at the intersection of hardware and software, shaping the platform from IP bring-up through full-chip validation — defining testbenches, authoring test firmware, and implementing critical SoC features in silicon. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.
Silicon Validation Engineer, HBM, Google Cloud Google LLCSilicon Validation Engineer, HBM, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Quality Engineer Oklo IncQuality EngineerSanta Clara, CA$150,000–$180,000 / yearThis role will work closely with Engineering, Procurement, Supplier Quality, Project Quality, suppliers, laboratories, and fabrication organizations to translate code and material requirements into practical controls; verify material specifications and test requirements; review and manage certified material test reports; support material traceability and special process controls; and develop a robust Certifying Engineer Program. Develop metrics, status reports, trend analyses, technical guidance, and training related to Code compliance, material acceptance, CMTR review, testing, supplier performance, and Certifying Engineer activities; communicate risks and recommended actions clearly to Engineering, Procurement, Quality, project leadership, suppliers, and other stakeholders.
Software Engineer III, Mobile (Android), YouTube Google LLCSoftware Engineer III, Mobile (Android), YouTubeSan Jose, CAhome home Home work_outline Jobs Jobs noogler_hat Students Students google How we work How we work handyman How we hire How we hire person_outline Your career Your career help_outline Help link feedback Send feedback more_vert Help Send Feedback Sign in. Careers Careers home home work_outline Jobs expand_more noogler_hat Students expand_more google How we work expand_more handyman How we hire expand_more person_outline Your career expand_more.
Staff Data Engineer, Search, Data Science Google LLCStaff Data Engineer, Search, Data ScienceMountain View, CAYou will work end-to-end to help build products that users love, enabling headroom analysis, experiment analysis, and technical trade-offs between competing metrics (e.g., richness of experience vs. Own the data engineering strategy for high-stakes Search initiatives, designing multi-stage data products that process data for billions of users.
Staff Software Engineer, AI and Infrastructure Google LLCStaff Software Engineer, AI and InfrastructureSunnyvale, CAThe Borglet Infrastructure group in Borglet is a team of 30 SWEs (distributed between Sunnyvale and Warsaw) developing core pieces of Borglet (Software Architecture, Runtime, Machine Management, Storage) to deliver the container infrastructure that is scalable, extensible, efficient and secure. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud.
Senior Software Engineer, Machine Learning, Core ML Google LLCSenior Software Engineer, Machine Learning, Core MLMountain View, CAExperience with deep learning frameworks (e.g., JAX, PyTorch, or TensorFlow), including a track record of contributing to or modifying their core internals to support novel and emerging use cases. Design and manage large-scale training runs across multi-pod environments, maximizing data center network bandwidth and minimizing communication bottlenecks.
Staff Software Engineer, Google Cloud Business Platforms Google LLCStaff Software Engineer, Google Cloud Business PlatformsSunnyvale, CACareers Careers home home_outline Jobs expand_more noogler_hat Students expand_more google How we work expand_more handyman How we hire expand_more person_outline Your career expand_more. home home Home home_outline work_outline Jobs Jobs noogler_hat noogler_hat Students Students googlegoogle.
Senior Mechanical Engineer TeradyneSenior Mechanical EngineerSan Jose, CA$121,700–$214,200 / yearThe candidate will be able to take product requirements and with minimal oversight, be able to develop detailed design solutions, be able to present to other design engineers and manufacturing engineers the proposed solution, perform DFM with vendors, and prepare final drawings and BOMs for fabrication. The ideal candidate would have a working knowledge and previous experience with some or all of the following topics: + Familiar with electrical connector design both for power delivery and high speed signal delivery.
Staff Robot Controls Integration Engineer Rhoda AIStaff Robot Controls Integration EngineerMountain View, CaliforniaOur robots are designed to be generalists capable of operating in complex, real-world environments and handling long-tail edge cases, made possible by our cutting edge research and end-to-end system design. This role sits at the intersection of embedded firmware, control theory, and hardware bringup: you'll validate control behavior across the full stack, diagnose timing and performance issues, and drive fixes that make our robots actually work .
RTL / Circuit IP Design Engineer Advanced Micro Devices, IncRTL / Circuit IP Design EngineerSan Jose, CaliforniaThe focus of this role is to plan, build, and execute the implementation of new and existing features for AMD’s programmable embedded IP, resulting in final designs that meet product defined power, performance, and area targets with intended functionality that operates on silicon and is modeled accurately for customer design use. Strong understanding of circuit design concepts, translating circuit designs in an optimal way to either custom implementations or with best practices for RTL synthesis .
Application Validation Engineer Super Micro Computer, Inc.Application Validation EngineerSan Jose, CA$89,000–$115,000 / yearThe individual will work with cross-functional engineering team to fix quality issues and ensure the products meet engineering and customer specifications, support Research and Development engineering and pre-and-post product release activities, such as white-box design verification, BIOS/IPMI testing on the board products, as well as on the system level, black-box testing. About Supermicro: Supermicro is a Top Tier provider of advanced server, storage, and networking solutions for Data Center, Cloud Computing, Enterprise IT, Hadoop/ Big Data, Hyperscale, HPC and IoT/Embedded customers worldwide.
Analog And Mixed Signal Design Engineer Intel Corp.Analog And Mixed Signal Design EngineerSanta Clara, CA$164,470–$269,100 / yearPreferred Qualifications: Experience in one or more of the following areas is preferred: GPIOs, high speed parallel or serial IO links and their subcomponents (data path, TX, RX, etc.), clock distribution, clock conditioning, clock recovery circuits, voltage regulators, voltage reference circuits, ADCs/DACs, inductors, transmission lines, RF and millimeter-wave circuits, test of custom analog and mixed-signal circuits. Business group: Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly.
Senior Optomechanical Engineer Lawrence Livermore National LaboratorySenior Optomechanical EngineerLivermore, CA$175,530–$222,564 / yearAn employee's position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, seniority, geographic location, performance, and business or organizational needs. Our mission spans four critical national security areas nuclear deterrence, threat preparedness, energy security, and multi-domain defense empowering teams to take on the toughest challenges of today and tomorrow.
NewAssociate Design Engineer DustPhotonics LtdAssociate Design EngineerSan Jose, CA$100,000–$150,000 / yearOur product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Our technology powers the most reliable and energy-efficient connections around the world - and our team powers new products and markets that come next.
NewSr Clinical Engineer Imperative CareSr Clinical EngineerCampbell, CAFull timeEnsure detailed plans are executed fully to support internal development projects with preclinical testing including bench testing, model development needs, in-vitro test methods and plans and in-vivo animal studies. Serve as a clinical engineering team member for product development including preclinical testing, bench testing, model development needs, in-vitro test methods and plans and in-vivo animal studies.
Internship, AI Hardware Silicon Validation Engineer, AI Hardware (Fall 2026) Tesla IncInternship, AI Hardware Silicon Validation Engineer, AI Hardware (Fall 2026)Palo Alto, CA$20–$55 / hourBy creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. As a Silicon Validation Engineer, the candidate will take on challenges like validating High-Speed Serdes, perform system level power characterization, and troubleshooting complex hardware bugs and field returns.
Post Silicon Validation Engineer, AI Hardware Tesla IncPost Silicon Validation Engineer, AI HardwarePalo Alto, CA$160,000–$282,000 / yearThe candidate will regularly take part in hardware design and schematics review, firmware development, and building automated test infrastructures for running large volumes of post-silicon system-level tests. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.
Staff HiL SW Infrastructure Engineer Agility Robotics IncStaff HiL SW Infrastructure EngineerFremont, CA$190,000–$247,000 / yearAgility's commercially deployed humanoids operate alongside teams in warehouses, manufacturing facilities, and distribution centers-tackling physically demanding and repetitive tasks while enabling workers to focus on higher-value work. Fault Injection Implementation: Programmatically control Fault Injection Units (FIU) to simulate short-to-battery, short-to-ground, and open-circuit conditions on critical robot signals.
PCB Layout Engineer Cowboy SpacePCB Layout EngineerSan Carlos, CaliforniaOur satellites operate in Low Earth Orbit to collect sunlight and enable a new class of capabilities—from powering on-orbit compute, to transmitting energy via infrared lasers (space-to-earth and space-to-space), powering on-orbit compute to delivering secure, high-bandwidth optical data. Export Control Requirement: To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR), applicants must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.
Senior RTL Engineer, Interconnect Design OpenAISenior RTL Engineer, Interconnect DesignSan Francisco, CaliforniaFor unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale.
Chief Systems Engineer (CSE) E-SpaceChief Systems Engineer (CSE)Saratoga, CA$190,000–$225,000 / yearWith Space Systems Electrical Engineering (SSEE) as an organic fifth function, the CSE also holds sole authority over the spacecraft-level electrical architecture and the electrical ICD framework to which every hardware VP and Semiconductor Development designs. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.
NewMission Systems Engineer E-SpaceMission Systems EngineerSaratoga, CA$100,000–$200,000 / yearVerification & Validation — building and executing the mission V&V plan, defining and tracking Technical Performance Measures (TPMs), planning environmental test campaigns (TVAC, vibration/acoustic, EMI/EMC), and dispositioning test data and anomalies for the assigned mission. Program and customer interface — serving as the technical point of contact to the government customer and Program Manager for the assigned contract; preparing for and presenting at contract technical reviews and milestones (e.g., SRR, PDR, CDR, TRR) and closing associated action items.
TPU Hardware Design Engineer, Cloud Google LLCTPU Hardware Design Engineer, CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. You will join the team designing and developing the on-chip network of Google"s next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in data centers.
TPU SoC Design Engineer, Cloud Google LLCTPU SoC Design Engineer, CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. You will work on top-level RTL, architecture, design and implementation of global communication busses, and integration of complex ASIC designs, as this is a highly cross-functional and central role that will require interactions with numerous ASIC development teams.
Senior TPU Validation Engineer Google LLCSenior TPU Validation EngineerMountain View, CAGoogle is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. Minimum qualifications: Bachelor"s degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.
Silicon Physical Design Engineer Google LLCSilicon Physical Design EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. You"ll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Senior Packaging Design Engineer, Silicon Google LLCSenior Packaging Design Engineer, SiliconMountain View, CA$163,000–$237,000 / yearCollaborate closely with Signal Integrity (SI), Power Integrity (PI), Test, New Product Introduction (NPI), and Mechanical Engineering teams to refine and optimize product package architecture and design. Skip navigation links home Home work_outline Jobs noogler_hat Students google How we work handyman How we hire person_outline Your career help_outline Help.
Senior RTL Design Engineer, TPU Google LLCSenior RTL Design Engineer, TPUSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Senior Design and Integration Engineer, Cloud TPU Google LLCSenior Design and Integration Engineer, Cloud TPUSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Join the team designing and developing the On-Chip Network of Google"s next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in datacenters.
Silicon Validation Engineer, Google Cloud Google LLCSilicon Validation Engineer, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Debug and help root-cause failures, providing feedback to improve features like power management quality, performance, and reliability through generations of designs, including in pre-silicon prototyping platforms as well as through post-silicon bringup and production.
Package Design Engineer Google LLCPackage Design EngineerSunnyvale, CAAdditionally, you will be instrumental in identifying and incorporating advanced chip packaging technologies into the Google chip product design pipeline, which contributes to successful chip deployment in data centers, ensuring the best optimized PPA (Power, Performance, Area) designs and enhancing system performance relative to TCO (Total Cost of Ownership) and power. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
TPU RTL Design Engineer Google LLCTPU RTL Design EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving team behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Senior Systems Engineer Santa Clara Valley Transportation AuthoritySenior Systems EngineerSan Jose, CA$165,053.24–$200,603.54 / yearUnique among transportation organizations in the San Francisco Bay Area, VTA is Santa Clara County's authority for transit development and operations (light rail and bus), congestion management, transportation-related funding, highway design and construction, real estate and transit-oriented development, and bicycle and pedestrian planning. The position works closely with maintenance teams, contractors, consultants, and other engineering disciplines, requiring strong technical judgment, project management capability, and the ability to deliver practical, effective solutions in a dynamic operating environment.
Senior Software Engineer, Embedded Security, Silicon Google LLCSenior Software Engineer, Embedded Security, SiliconMountain View, CAApplyshare linkCopy linkemailEmail a friendinfo_outlineXNote By applying to this position you will have an opportunity to share your preferred working location from the following Mountain View CA USA San Diego CA USA.Minimum qualificationsBachelors degree or equivalent practical experience.5 years of experience with software development in one or more programming languages e.g. Were looking for engineers who bring fresh ideas from all areas including information retrieval distributed computing large-scale system design networking and data storage security artificial intelligence natural language processing UI design and mobile the list goes on and is growing every day.
Senior TPU RTL Design Engineer, Networking, Inter-Chip Interconnects Google LLCSenior TPU RTL Design Engineer, Networking, Inter-Chip InterconnectsSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Join the team designing and developing the core components of Google"s next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in data centers.
TPU SoC Design Engineer, Google Cloud Google LLCTPU SoC Design Engineer, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.