ASIC/RTL Design Engineer 5

Job Title: ASIC/RTL Design Engineer 5
Location: San Jose, CA 95124
Duration: 12 Months
Job Type: Temporary Assignment
Work Type: Onsite

Job Description:

• You will build behavioral models of analog and mixed-signal circuits (PLLs, clocking, ADC/DAC, TX/RX analog front ends, calibration loops) in SystemVerilog.
• Those models drop into a SystemVerilog UVM verification environment used for high-speed SerDes and SoC IP.
• You will work closely with analog circuit designers, RTL designers and verification engineers.
• Successful candidates will be responsible for leading, and participating in, the modeling and verification of leading-edge designs in advanced CMOS processes.
• Our modeling engineers are expected to contribute in all of the following areas:
• Reading schematics, netlists and circuit specifications to define what each model must capture.
• Developing model architecture and accuracy targets, balancing fidelity against simulation speed.
• Writing behavioral SystemVerilog models of analog blocks.
• Validating models against transistor-level simulation results.
• Debugging simulation failures and finding the root cause in the model, RTL or testbench.
• Documenting model behavior, limitations and interfaces.

Experience and Education:

• Hands-on experience writing behavioral models of analog circuits in SystemVerilog.
• Working knowledge of analog and mixed-signal circuit fundamentals and of the SystemVerilog UVM methodology, with proven skill debugging failures in simulation and waveforms.
• Familiarity with high-speed interface standards is a plus.