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IonQ’s newest generation of quantum computers, the IonQ Tempo, is the latest in a line of cutting-edge systems that have been helping customers and partners including Amazon Web Services, and AstraZeneca achieve 20x performance results and accelerate innovation in drug discovery, materials science, financial modeling, logistics, cybersecurity, and defense. Define and implement controlled impedance structures (microstrip, stripline, and differential pairs), signal integrity strategies, power distribution networks, grounding schemes, and EMI/EMC-aware layout practices.

YEAR

Vector Atomic

Senior Staff Engineer - Electrical

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System Design: Architect and design complex wiring harnesses that interface Teleo's autonomy kit with OEM construction equipment, utilizing schematics, service manuals, diagnostic analysis, and vehicle signal characterization to integrate with existing machine systems. Documentation & Scaling: Author comprehensive schematics, Bills of Materials (BOMs), installation manuals, and training assets to enable scalable, repeatable deployments by field teams.

Teleo

Electrical Integration Engineer

HOUR

You will take ownership from concept through production, working cross-functionally with electrical, systems, and manufacturing engineers to deliver high-performance, reliable hardware. You will design robust mechanical systems while integrating power distribution, wiring, and high-voltage components into complex semiconductor test equipment.

Artech LLC

Sr. Electro-Mechanical Engineer

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The team delivers architecture and logic implementation of digital modules with a strong focus in high-throughput low-power digital signal processing (DSP). These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.

Neuralink

Digital Verification Engineer

This is a highly visible technical and leadership role where you will influence DFT architecture, lead complex execution across teams, drive methodology improvements, mentor engineers, and support successful silicon bring-up, yield ramp, and production quality. Experience developing DFT methodologies for low-power designs, including UPF-aware test strategies, power domain testing, isolation, retention, and test-mode power management.

Velaura

DFT Engineer (Architect / Manager / Sr. Manager)

You will apply that expertise to studying and improving the performance and power behavior of modern System-on-Chip designs across the full product lifecycle: ML-driven research to identify what should change in hardware or software, hands-on partnership with silicon and OS teams to implement and bring those changes up on real silicon, and seeing them through to ship. The work targets the full performance-power tradeoff space across fabric, memory subsystem, system caches, dynamic voltage and frequency state control, clock and power gating policies, sleep state controls, and bottleneck prevention.

<div class="col-md-4 passion" style="background-color: #666666; border-radius: 20px; -webkit-box-shadow: 2px 2px 2px 2px #979b91; -moz-box-shadow: 2px 2px 2px 2px #979b91; box-shadow: 2px 2px 2px 2px #979b91; color: #ffffff; font-family: calibri; font-size: 13px; padding: 17px; text-align: center;">
<h3 style="color: #ffffff; font-size: 16px; font-weight: normal;">We bring amazing people together to make amazing things happen.</h3>
<p>We’re a diverse collection of thinkers and doers, continually reimagining what’s possible to help us all do what we love in new ways. The people who work here have reinvented entire industries with the Mac, iPhone, iPad, and Apple Watch, as well as with services, including iTunes, the App Store, Apple Music, and Apple Pay. And the same passion for innovation that goes into our products also applies to our practices — strengthening our commitment to leave the world better than we found it.</p>
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<h3 style="color: #666666; font-weight: 500;">About Apple</h3>
<p>There’s a place here for every kind of brilliant.
Everyone here is an innovator, or an innovator-to-be, no matter what your team or your role. So bring your passion, courage, and original thinking and get ready to share it, because every new product, service, or feature we invent is the result of people working together to make each others’ ideas stronger. Innovation at this level depends on people who represent the variety of the human experience and inspire us with their own fresh perspectives. Together, we’ll do amazing work that can make a difference in people’s lives. Including your own.

<a href="https://www.apple.com/jobs/us">Learn more about working at Apple.</a>
</p>
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Apple Inc

Applied Machine Learning Engineer, Platform Architecture

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This is a great opportunity to be at the focal point of many cross-functional interactions with Apples internal hardware/software teams, contract manufacturer teams, and IC vendor teams throughout different development stages. The iPhone Division is seeking an enthusiastic Analog Design Engineer to join a creative and energetic engineering team developing future iPhone products.

iPhone Analog Design Engineer

You will design and conduct performance experiments, create instrumentation and data visualizations, prototype innovative in-kernel performance control algorithms, collaborate with teams ranging from the core operating system through user-facing applications, and productize the software that controls the performance of every workload executed on hundreds of millions of Apple products around the world. In this position, you will study the execution of workloads on Apple silicon across all Apple platforms and leverage that understanding to invent new operating system performance control features.

Performance Control Software Engineer - Platform Architecture

OTHER

End-to-End RTL2GDS Ownership  Own the full RTL2GDS flow on advanced process nodes — synthesis, floorplan, placement, CTS, routing, and signoff — across Astera's connectivity product portfolio  Drive block- and chip-level place & route strategy, congestion resolution, and routing convergence on high-frequency, high-density designs  Architect clock tree synthesis and clocking topology to meet skew, latency, and power targets  Lead tapeout execution: final ECO closure, GDS handoff, and post-tapeout support through fab  Timing, Power & Signoff  Drive multi-mode multi-corner STA closure, low-power implementation (UPF/CPF), and IR/EM analysis to signoff  Own physical verification (LVS, DRC, antenna, ERC) and reliability signoff through clean closure  Define methodology for ECO flows, hierarchical timing, and full-chip signoff sign-around  Technical Leadership & Cross-Functional Partnership  Partner with RTL, DFT, analog/mixed-signal, package, and CAD teams to converge on floorplan, clocking, and power delivery strategies  Establish and evolve physical design methodology, scripts, and flows across the team  Mentor engineers, drive design reviews, and represent Physical Design in program-level technical decisions  Basic Qualifications  . MS in Electrical Engineering or Computer Engineering  Experience with high-speed SerDes-heavy designs, PCIe Gen 6/7, or UALink/UCIe-based connectivity SoCs  Hands-on experience with hierarchical implementation and full-chip integration of large designs (>500M gates)  Familiarity with EMIR, thermal, and package co-design considerations  Experience mentoring senior engineers and driving methodology adoption across teams  Salary range is $185,000 to $240,000 depending on experience, level, and business need.

Astera Labs

Principal Physical Design Engineer

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Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 3-5 years of relevant hardware engineering experience, or a master's degree or PhD in a related field with 2-3 years of relevant experience. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.

Marvell Technology Inc

Staff Hardware Engineer, Optics

Not satisfied by superficial explanations of a problem or “band-aid engineering”; seeks persistently to find the specific root cause through data-driven methods, and resolve failures or recurring issues, so they can be mitigated to prevent future such instances. Gratified by helping your peers succeed, building a robust team culture, and propagation deep camaraderie amongst your peers; seeks to break down information silos by collaborating rigorously with others to solve problems, share knowledge, and provide input.

Chariot Defense

Software Engineer, Systems

The company's next-generation batteries are designed to enable greater energy density, faster charging and enhanced safety to support the transition away from legacy energy sources toward a lower carbon future. As an on-site R&D and manufacturing operations organization, in-person face to face interaction is essential to building authentic relationships, trust, teamwork, and collaboration.

QuantumScape Corp.

Staff Hardware Engineer, Battery Systems

You will define heat rejection architectures, design radiators and conduction paths, and run thermal vacuum campaigns, working closely with RF, electrical, mechanical, and systems engineers to make sure the hardware survives and performs on orbit. To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.

Array Labs

Thermal Engineer

Hardware Engineer, Battery Systems

As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII.Generate block/chip level static timing constraints. In this role, we will be at the center of a PHY design effort working with architecture, CAD, timing and logic design teams, with a critical impact on delivering outstanding PHY designs.

Physical Design Engineer

Drive fleet robustness by confirming every node recovers to a known safe state without manual intervention after failed or interrupted updates, power loss during flashing, corrupted images and watchdog resets, backed by long-duration soak and stress testing. Build hardware-in-the-loop (HIL) test rigs, from single boards to full actuator and robot setups, with fault injection for power, communication and sensor failures and validation of real-time buses (EtherCAT, CAN/CAN FD, SPI, UART, I2C).

1X Technologies

Firmware Engineer - Testing

At Nextpower, we are driving the global energy transition with an integrated clean energy technology platform that combines intelligent structural, electrical, and digital solutions for utility-scale power plants. Our talented worldwide teams are redefining how solar power plants are designed, built, and operated every day with smart technology, data-driven insights, and advanced automation.

Nextracker Inc.

Autonomy Engineer

Knowledge or experience in designing digital and power circuits, high-speed circuit layout, energy storage and motion control, H-bridge circuitry, and various power circuit topologies such as buck, boost, buck-boost, flyback, SEPIC and variant topologies, is preferred. The Electronics Hardware team within the Technology and Breakthrough Innovation group is seeking a Senior Engineer with in-depth technical expertise in analog circuit design, including high precision analog/other circuits used in signal conditioning and processing.

Delaney Group

Senior Engineer

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Top-notch engineering intuition and first principles thinking toward designing complex products that function seamlessly for your customer, taking both an engineering/ technical, and product/ customer approach, to strike the optimal balance. Not satisfied by superficial explanations of a problem or “band-aid engineering”; seeks persistently to find the specific root cause through data-driven methods, and resolve failures or recurring issues, so they can be mitigated to prevent future such instances.

Software Engineer, Embedded Linux

Individual compensation decisions are based on a number of factors, including but not limited to previous experience and skills acquired prior to joining Syntiant, cost of living in the assigned work location, assigned schedule, and salaries of similarly situated peers at the company. The company’s purpose-built silicon and hardware-agnostic models are being deployed globally to power edge AI speech, audio, sensor and vision applications across a wide range of consumer and industrial use cases, from earbuds to automobiles.

Power Engineer Jobs in San Jose, CA

Senior Staff Engineer - Electrical Vector Atomic

Electrical Integration Engineer Teleo

Sr. Electro-Mechanical Engineer Artech LLC

Digital Verification Engineer Neuralink

DFT Engineer (Architect / Manager / Sr. Manager) Velaura

Applied Machine Learning Engineer, Platform Architecture Apple Inc

iPhone Analog Design Engineer Apple Inc

Performance Control Software Engineer - Platform Architecture Apple Inc

Principal Physical Design Engineer Astera Labs

Staff Hardware Engineer, Optics Marvell Technology Inc

Software Engineer, Systems Chariot Defense

Staff Hardware Engineer, Battery Systems QuantumScape Corp.

Thermal Engineer Array Labs

Hardware Engineer, Battery Systems QuantumScape Corp.

Physical Design Engineer Apple Inc

Firmware Engineer - Testing 1X Technologies

Autonomy Engineer Nextracker Inc.

Senior Engineer Delaney Group

Software Engineer, Embedded Linux Chariot Defense

Field Applications Engineer Syntiant

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