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What you will be doing: Own validation of products from start to finish including test plan development, automation, design for validation requirements, resource planning, coverage metrics, test execution, bug resolution, and release to production. In this role you will be working with a team of HW/SW engineers to develop and implement complex automated test plans for our industry leading GPU accelerated computing products.

Visualize your future . . . We Do 
NVIDIA is the world leader in graphics processing technologies, creating innovative, industry-changing products for computing, consumer electronics, and mobile devices. NVIDIA products are transforming visually-rich applications such as video games, film production, broadcasting, industrial design, space exploration, and medical imaging. We invest in our people and our technologies, support and fund industry research around the world, and consistently deliver high-quality products. NVIDIA's culture promotes and inspires a team of world-class employees to be at the top of their game. We've created an environment where talents are recognized and collaboration is valued. Our employees are shaping the world of tomorrow. . . today. We invite you to explore the opportunities available at NVIDIA to see what your future may hold.

Nvidia

Senior High Speed Serdes Validation Engineer

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We work in environments where labeled data is limited and proprietary, distributions shift across tools and fabs, production budgets are tight, and software must operate inside air-gapped facilities. Design agentic workflows for air-gapped fabs that connect data triage, model inference, review assistance, root-cause analysis, human approval, and secure deployment.

Principal Systems Software Engineer, Semiconductor Systems Inspection

Fandom Productions, the content arm of Fandom, enhances the fan experience through curated editorial coverage and branded content from trusted and established publishing brands Gamespot, TV Guide and Metacritic, along with its Emmy-nominated Honest Trailers and the weekly video news program The Loop. Reaching more than 350 million unique visitors per month and hosting more than 250,000 wikis, Fandom is the #1 source for in-depth information on pop culture, gaming, TV and film, where fans learn about and celebrate their favorite fandoms.

YEAR

Fandom, Inc.

Senior Cloud Engineer

What we need to see: BS (or equivalent experience) in Electrical Engineering, Computer Engineering, or related fields with 12+ years of experience, or MS with 10+ years of proven experience in FPGA prototyping. The expected base salary ranges for this position are: 196,000 USD - 310,500 USD for Level 5; and 232,000 USD - 368,000 USD for Level 6.

Senior Fpga Prototyping Engineer - Hardware

The expected base salary ranges for this position are:152,000 USD – 241,500 USD for Level 3; and 184,000 USD – 287,500 USD for Level 4. You will also be eligible for equity and benefits . Design, develop and verify features for our next generation SoC architecture, collaborating with hardware engineers and fellow software engineers.

NVIDIA

Tegra System Software Engineer

You will be an integral part of a team that delivers features and improvements to better realize the potential of NVIDIA hardware for a growing range of computational workloads, ranging from deep learning, scientific computation, data science and self-driving cars to video games and virtual reality. More recently, GPU deep learning ignited modern AI — the next era of computing — with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world.

Senior Software Engineer, CUDA UMD - Graphs and GPU Sharing

Lead end‑to‑end performance and scalability analysis across the Kubernetes‑based accelerated runtime stack (control and data planes), including NVIDIA components such as GPU Operator, Network Operator, node-feature-discovery, topograph, dra-driver-nvidia-gpu, and nvsentinel, tracking issues from orchestration down to the metal. Improve container startup and cold‑start latency to enable smooth, low‑latency inference scaling on Kubernetes across thousands of GPU nodes, ensuring the AI runtime stack scales without creating API server pressure or operational fragility.

Senior Systems Software Engineer, Accelerated Kubernetes Performance and Scale - DGX Cloud

We are seeking software engineers with interests in designing, developing and maintaining many aspects of the core technology around sensor drivers and interfaces, data streaming, data recording and playback, and vehicle interface abstraction. The expected base salary ranges for this position are:184,000 USD – 287,500 USD for Level 4; and 224,000 USD – 356,500 USD for Level 5.

Senior System Software Engineer - Autonomous Vehicles

You will work as part of a team to design and implement high speed interfaces and complex mixed-signal circuits using state-of-the-art sub-micron CMOS technologies and various EDA tools: High speed analog and hybrid Phase Locked loops and associated subblocks including VCO, charge-pump, dividers, state machines, LDO, bandgap, TDC, interpolator circuits, high speed buffers etc. Your other responsibilities will include architecture studies, circuit designs & simulations, floor-planning, instructing mask designers, reliability verifications and silicon bring-up.

Senior Analog and Mixed Signal Engineer

Able to communicate effectively to technical and non-technical audiences at all levels in the organization; develop procedural documentation; develop and conduct effective presentations; and effectively demonstrate products and solutions. Our Event Tech Ops team powers the technology behind hundreds of NVIDIA events worldwide each year-from major moments like CES and GTC to CEO Keynotes, product launches, demos, and everything in between.

Event Tech Ops Engineer

We are looking for a Senior Software Engineer to join the cuEquivariance team - an NVIDIA library that accelerates geometric neural networks on NVIDIA GPUs, enabling researchers in molecular biology, materials science, and physics to train and deploy equivariant models at scale. What You Will Be Doing: Build, implement, and optimize CUDA kernels for equivariant neural network primitives - tensor products, segmented polynomials, and triangle-based operations - targeting peak performance across NVIDIA GPU generations.

Senior Software Engineer - Cuequivariance

Certain information you provide as part of the application will be used for purposes of determining whether Intuitive Surgical will need to (i) obtain an export license from the U.S. Government on your behalf (note: the government's licensing process can take 3 to 6+ months) or (ii) implement a Technology Control Plan ("TCP") (note: typically adds 2 weeks to the hiring process). U.S. Export Controls Disclaimer: In accordance with the U.S. Export Administration Regulations (15 CFR §743.13(b)), some roles at Intuitive Surgical may be subject to U.S. export controls for prospective employees who are nationals from countries currently on embargo or sanctions status.

Intuitive Surgical

Sr Software Engineer, Planpoint

In this role, you will work together with other developers on developing solutions that involve generalizations to sparse tensor computations, domain specific language (DSL) specifications of sparse storage formats, and on-demand code generation. Ideal candidates will not only have experience developing accelerated computing software, but also be motivated to advance the state-of-the-art in a variety of accelerated computing domains and DL frameworks like PyTorch.

Senior Math Libraries Engineer - Sparsity in AI

As a Senior DFT - Silicon Validation Engineer, you will work on ground breaking technologies in DFT to accelerate and left shift silicon validation of the most complex semiconductor chips. Your tasks include planning from architecture and development, performing chip validation on ATE, debugging test content, and analyzing silicon behavior under various operating conditions.

Senior DFT - Silicon Validation Engineer

Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.

Senior Asic Design Engineer - Clocks IP

Integrate building management systems (BMS), electrical power monitoring systems (EPMS), and equipment controls, ensuring systems respond accurately during normal operation and recovery. Coordinate liquid-cooling interfaces from facility water systems through coolant distribution units (CDUs), technology cooling loops, manifolds, and rack connections, ensuring compatibility and reliability.

DSX Infrastructure Integration Engineer

We are looking for a Principal Photonics IC Design Engineer to serve as the technical lead owning our photonics integrated circuit (PIC) product — from architecture definition through production tapeout and silicon validation. PhD in Electrical Engineering, Physics, Applied Physics, or a closely related field with emphasis on integrated photonics, silicon photonics, or photonic device physics (or equivalent experience).

Principal Photonics IC Design Engineer

Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc. The expected base salary ranges for this position are:116,000 USD – 189,750 USD for Level 2; and 136,000 USD – 218,500 USD for Level 3.

ASIC Physical Design Engineer, Netlisting - New College Grad 2026

Experience leading multi-team initiatives across geo/time zones, with clear examples of influence without authority as well as eager and proactive in bringing to bear AI-powered tools to accelerate debugging, documentation, and day-to-day engineering efficiency while maintaining strong engineering judgment. Partner with internal engineering, product, and architecture teams to transform customer needs into product features, reference architectures, tooling, and guidelines.

Senior Software Engineer, AI Networking

Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation. What you'll be doing: Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level.

Game Engineer Jobs in San Mateo, CA

Senior High Speed Serdes Validation Engineer Nvidia

Principal Systems Software Engineer, Semiconductor Systems Inspection Nvidia

Senior Cloud Engineer Fandom, Inc.

Senior Fpga Prototyping Engineer - Hardware Nvidia

Tegra System Software Engineer NVIDIA

Senior Software Engineer, CUDA UMD - Graphs and GPU Sharing NVIDIA

Senior Systems Software Engineer, Accelerated Kubernetes Performance and Scale - DGX Cloud NVIDIA

Senior System Software Engineer - Autonomous Vehicles NVIDIA

Senior Analog and Mixed Signal Engineer NVIDIA

Event Tech Ops Engineer Nvidia

Senior Software Engineer - Cuequivariance Nvidia

Sr Software Engineer, Planpoint Intuitive Surgical

Senior Math Libraries Engineer - Sparsity in AI NVIDIA

Senior DFT - Silicon Validation Engineer NVIDIA

Senior Asic Design Engineer - Clocks IP Nvidia

DSX Infrastructure Integration Engineer Nvidia

Principal Photonics IC Design Engineer NVIDIA

ASIC Physical Design Engineer, Netlisting - New College Grad 2026 NVIDIA

Senior Software Engineer, AI Networking Nvidia

Asic Physical Design And Timing Engineer - New College Grad 2026 Nvidia

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