Day-to-day work includes Civil 3D modeling, earthwork calculations, and preparing SWMPs, drainage studies, and utility reports alongside an experienced engineering team.
For additional information regarding the Benefit programs available, please see the Benefits Guide posted onmicron.com/careers/benefits. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
For additional information regarding the Benefit programs available, please see the Benefits Guide posted onmicron.com/careers/benefits. This position involves contributing to array architecture definition and analysis, as well as leading the design of analog, basic digital, and mixed-signal circuits for advanced memory technologies including DRAM and Emerging memories.
p>Business group: The Central Engineering Group (CEG) is Intel''s data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies).
Variable incentives may also be offered." Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html.
Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.
p>Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge any candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html.
Rooted in our distinct culture of Truly Human Leadership, we cultivate the leaders who will define tomorrow and partner with our clients in the food & beverage, life sciences, industrial, and advanced technology industries to build the future of manufacturing and technology. By blending people-centric leadership with disciplined operational strategies and purpose-driven growth, Barry-Wehmiller has become a $3 billion organization with nearly 12,000 team members united by a common belief: to use the power of business to build a better world.
For additional information regarding the Benefit programs available, please see the Benefits Guide posted onmicron.com/careers/benefits. The US base salary range that Micron Technology estimates it could pay for this full-time position is: $177,000.00 - $309,000.00 a year.
p style="margin:0px">As a SYSTRA US Civil Design Engineer you will join a world-class team of high-performing engineers, designers, drafters and others who work collectively to ensure client projects continue to thrive while remaining on track and budget. We partner with public transportation owners and operators of bridges, buses, commuter and intercity, high-speed and light rail, mass rapid transit and tunnels, helping them provide safe, efficient and reliable public transportation.
p>• Lead evaluation of architectural trade-offs considering features, performance targets, power constraints, and system limitations • Define and document micro-architecture for complex SoC IP blocks; implement RTL in Verilog/SystemVerilog, integrate at top level, and deliver fully verified, synthesis- and timing-clean designs • Collaborate closely with verification teams to ensure comprehensive coverage and robust validation of all design aspects • Develop and maintain timing constraints for IP blocks; provide guidance and support to physical design teams for synthesis, timing closure, and formal equivalence checks • Drive silicon bring-up and post-silicon validation, including debug and performance analysis • Mentor junior engineers and contribute to best practices for design methodology and quality. Find more information about all of our Amazing Benefits here: https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003.
The team is responsible for all SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN verification, Quality Assurance, Layout Verification etc. A successful candidate will have proven experience demonstrating the following skills and behavioral traits: The ideal candidate will be capable of leading a small team as well as interacting with architecture and design teams to improve IP and ultimate product quality and performance.
p>Minimum Qualifications: The candidate must possess a bachelor's degree in computer engineering, Computer Science or Electrical/Electronic Engineering or any STEM related degree and 6+ years of experience OR master's degree in computer engineering, Computer Science or Electrical/Electronic Engineering or any STEM related degree and 4+ yrs.
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