Design Engineer Jobs in Roseville, CA

Day-to-day work includes Civil 3D modeling, earthwork calculations, and preparing SWMPs, drainage studies, and utility reports alongside an experienced engineering team.

For additional information regarding the Benefit programs available, please see the Benefits Guide posted onmicron.com/careers/benefits.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

For additional information regarding the Benefit programs available, please see the Benefits Guide posted onmicron.com/careers/benefits. This position involves contributing to array architecture definition and analysis, as well as leading the design of analog, basic digital, and mixed-signal circuits for advanced memory technologies including DRAM and Emerging memories.

p>KEY RESPONSIBILITIES:

• Driving technical innovation to improve AMDs capabilities across functional and/or Performance validation, including tool and script development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives.
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues in the SOC (System on a Chip) programs bring-up, validation, and production phases.

With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. Our Loihi series of research chips pioneered event-driven, sparse, and massively parallel neuro-inspired processing, fueling over 100 peer-reviewed publications that validate the promise of this novel approach.

p>Business group:

The Central Engineering Group (CEG) is Intel''s data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). Your work will impact Intel''s success by delivering high-quality IP blocks and subsystems for seamless integration into full-chip designs, enabling superior power, performance, and efficiency in Intel''s products.

p>Minimum Qualifications:

• The candidate must possess a bachelor's degree in computer engineering, Computer Science or Electrical/Electronic Engineering or any STEM related degree and 2+ years of experience OR master's degree in computer engineering, Computer Science or Electrical/Electronic Engineering or any STEM related degree and 1+ years of experience.
• Possesses CPU-specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT.

p>Minimum Qualifications:

• The candidate must possess a bachelor's degree in computer engineering, Computer Science or Electrical/Electronic Engineering or any STEM related degree and 6+ years of experience OR master's degree in computer engineering, Computer Science or Electrical/Electronic Engineering or any STEM related degree and 4+ years of experience.

  Additional Locations:

  Business group:

  Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

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Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary Location: US, California, Folsom

Additional Locations: US, California, Santa Clara, US, Oregon, Hillsboro, US, Texas, Austin

Business group: Intel makes possible the most amazing experiences of the future.

Verification & Validation • Work closely with verification teams to achieve full coverage and robust validation • Develop timing constraints for IP blocks and assist physical design teams with synthesis, timing closure, and formal equivalence checks • Support silicon bring-up and post-silicon validation activities, including debug and performance analysis.

Day-to-day work includes Civil 3D modeling, earthwork calculations, and preparing SWMPs, drainage studies, and utility reports alongside an experienced engineering team. TAIT’s Rancho Cordova, CA office seeks a Civil Design Engineer to support land-development projects from preliminary layout through final plan production.

p>Specific skills required: The following skills are required:

Position requires four (4) years of experience in the following:

• Performing hardware verification and implementing comprehensive verification strategies;
• Design flows and methodologies used for chip verification;
• Creating test benches;
• Verilog, System Verilog, or UVM;
• C, C++, or Python;
• SoC, CPU, or GPU architecture; and.

  Alternate combination of education and experience: Employer will alternatively accept a Bachelor's degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronics Engineering, or related field and six (6) years of experience in the job offered or closely related engineering role.

Variable incentives may also be offered."

Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html.