p>Qualifications: A successful candidate will have proven experience demonstrating the following skills and behavioral traits:
• Bachelors in Electrical/Computer Engineering with 15+ years relevant work experience, or Masters in Electrical/Computer Engineering with 12+ years relevant work experience • The ideal candidate will be capable of leading a small team as well as interacting with architecture and design teams to improve IP and ultimate product quality and performance • Experience in: Logic Design, VLSI/ASIC Design, Computer Architecture • Current Industry Experience in one or more ASIC style design flows - floorplanning, clock construction, synthesis, place and route, static timing analysis, layout verification • Experience with Unix/Linux, Perl, and TCL in order to implement useable, flexible cshell/perl/tcl programs that automate tool/flow methodologies.
Responsibilities:
The team is responsible for all SoC level physical design and optimization flows ranging from Floor-planning, Clocking, Synthesis through GDS and parallel verification aspects such as Static Timing Analysis, Formal Verification, EM/IR/PDN verification, Quality Assurance, Layout Verification, etc.