ASIC Design Verification Engineer Palo Alto Networks IncASIC Design Verification EngineerSanta Clara, CA$106,400–$172,150 / yearYour Experience BS in EE, CE, or CS required or equivalent military experience required - MSEE preferred Minimum 3 years experience in ASIC design verification Demonstrated success in taking multiple ASIC products from concept to mass production Expertise in SystemVerilog and UVM Technical strength in the following areas is requiredDefining test plans, including comprehensive adversarial testing Developing rich functional coverage models Creating powerful and scalable test benches Implementing sophisticated self-checking infrastructure with reference models and scoreboards Developing reusable constrained-random tests Debugging failures Closing coverage Experience in the following areas is preferredNetworking and cyber security Formal property verification Silicon validation - bringup, test, debug, and regression Creating models in Python and C/C++ Writing driver code in C Skilled in writing powerful, modular, and scalable programs in Python, Perl, and UNIX shell to automate verification tasks, especially regression testing Demonstrated ownership and independence in planning, debugging complex failures, closing metrics-driven tasks, driving vendors, and reporting status Strong leadership, collaboration, and communication skills. Your Impact Collaborate with engineers in software, architecture, design, and verification teams to create comprehensive pre-silicon verification plans across simulation, emulation, and formal verification Plan and execute every aspect of simulation test plans using sophisticated coverage-driven, constrained-random methodologies Develop flows, methodologies, and infrastructure for emulation - Create, run, and debug emulation tests in close collaboration with system architects, software engineers, and ASIC designers Define new tools and methodologies to continuously improve quality and velocity Create powerful programs in Python to automate triage, coverage closure, and metrics-driven verification.
R&D Engineer IC Design Broadcom IncR&D Engineer IC DesignSan Jose, CA$120,000–$192,000 / yearResponsibilities will include creating SystemVerilog-based verification environments (testbenches, checkers, transactors) as well as creating and executing testplans for verifications of RTL and gatesim-based designs at both the block and chip level. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
Senior Datacenter Power Design And Modeling Engineer NvidiaSenior Datacenter Power Design And Modeling EngineerSanta Clara, CAThis role owns rack-level architecture definition and involvement, end to end power modeling and simulation for advanced Datacenter power and energy scheme, and power shelves, busbars, cable vendor management. You ensure the successful delivery of power-related engineering programs by modeling and simulation efforts, coordinating across power architects, power validation, firmware, mechanical teams, and suppliers management.
Asic Design Engineer NvidiaAsic Design EngineerSanta Clara, CAWhat you'll be doing: Drafting microarchitecture documents and implementing high-performance, and area and power-efficient RTL to meet strictly defined development targets and specifications. Collaborating closely with architects, other designers, and pre and post silicon verification teams to deliver world-class RTL builds.
NewSenior Hardware Design Engineer for AI Inference ASICs TensordyneSenior Hardware Design Engineer for AI Inference ASICsSan Jose, CAThe successful candidate will handle schematic design and PCB layout, collaborate with teams, and ensure compliance and testing for innovative hardware solutions. Emphasizing a supportive team atmosphere, Tensordyne offers competitive compensation and a dynamic work environment.#J-18808-Ljbffr.
NewHardware Design Engineer - AI Inference Hardware TensordyneHardware Design Engineer - AI Inference HardwareSunnyvale, CAThe ideal candidate will have a B.S. in Electrical or Computer Engineering and at least 2 years of relevant hardware engineering experience, particularly in schematic capture, PCB design, and hardware bring-up.#J-18808-Ljbffr. Tensordyne in Sunnyvale, California is searching for a Hardware Design Engineer to take ownership of hardware system development for cutting-edge AI Inference products.
NewSenior Hardware Design Engineer, AI Inference Systems TensordyneSenior Hardware Design Engineer, AI Inference SystemsSunnyvale, CAYou will collaborate closely with ASIC, software, and operations teams to define hardware requirements and deliver industry-leading solutions. This role offers the chance to own critical aspects of schematics, PCB layout, and mechanical design, ensuring high-performance AI products.
NewSenior Datacenter Power Design and Modeling Engineer NvidiaSenior Datacenter Power Design and Modeling EngineerSanta Clara, CAThis role owns rack‑level architecture definition and involvement, end to end power modeling and simulation for advanced Datacenter power and energy scheme, and power shelves, busbars, cable vendor management. You ensure the successful delivery of power‑related engineering programs by modeling and simulation efforts, coordinating across power architects, power validation, firmware, mechanical teams, and suppliers management.
NewAsic Physical Design And Timing Engineer - New College Grad 2026 NvidiaAsic Physical Design And Timing Engineer - New College Grad 2026Santa Clara, CAHelp in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation. What you'll be doing: Drive Physical Design and timing analysis and closure of NVIDIA's GPUs, CPUs, DPUs and SoCs at block level, cluster level, and/or full chip level.
Principal Design Verification Engineer Astera Labs IncPrincipal Design Verification EngineerSan Jose, CA$185,000–$230,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Design Verification Engineer, Staff Astera Labs IncDesign Verification Engineer, StaffSan Jose, CA$160,000–$195,000 / yearUsing your expertise in SystemVerilog, UVM, and problem-solving skills, youll contribute to the functional verification of cutting-edge designs supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. Youll be responsible for the full verification lifecycle-from planning to test development to debugging and coverage closure-while collaborating with RTL designers and system validation teams.
Technical Lead Design Verification Engineer Astera Labs IncTechnical Lead Design Verification EngineerSan Jose, CAAstera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Sr. Software Development Engineer (Applied ML)-Hardware Product Design Apple IncSr. Software Development Engineer (Applied ML)-Hardware Product DesignSunnyvale, CAYou'll join the Data Science and Visualization (DataViz) team in Hardware Engineering at Apple, working day-to-day in close partnership with Apple's Advanced Development Lab (ADL) to bring machine learning into the heart of their machining and prototyping workflows. Hands-on experience designing or extending agentic AI systems (multi-step, tool-using workflows where models plan, act, and recover) and the evaluation frameworks that keep them reliable - including ground truth that is contested, expensive, or partial, and small labeled datasets.
Timing Design Engineer Apple IncTiming Design EngineerCupertino, CAYou will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints.
NewPrincipal Design Verification Engineer Astera LabsPrincipal Design Verification EngineerSan Jose, CA$185,000–$230,000 / yearAstera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
NewLead Power & Board Design Engineer for ASICs Astera LabsLead Power & Board Design Engineer for ASICsSan Jose, CA$209,000–$230,000 / yearThis role involves designing and optimizing power systems for ASIC products, ensuring robust power integrity. Candidates should have 8-10 years of experience in power and board design engineering, and be proficient in Cadence OrCAD and Allegro.
NewLead Hardware Design Engineer, Server Motherboards supermicroLead Hardware Design Engineer, Server MotherboardsSan Jose, CAThe role requires strong x86 hardware expertise, high-speed signal integrity, and power regulation know-how, with hands-on PCB design and debugging skills, plus leadership potential within 12 months.#J-18808-Ljbffr. Hardware Design Engineer to drive development of in-house server motherboards, collaborating with cross-functional teams and external partners to ensure robust, high-performance board designs.
NewStaff Product Design Engineer NicedesignjobsStaff Product Design EngineerSan Francisco, CA$198,000–$233,000 / yearStaff Product Design Engineer Location: Hybrid - San Francisco, CaliforniaAbout Oura Our mission at Oura is to empower every person to own their inner potential. The company's award-winning products help users understand their readiness, activity, and sleep quality through the Oura Ring and connected app.
Principle Design Verification Engineer SerDes/PHY Astera Labs IncPrinciple Design Verification Engineer SerDes/PHYSan Jose, CA$207,000–$230,000 / yearYou''ll partner directly with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks that ship into the world''s most advanced AI platforms, including UALink, UCIe, PCIe Gen 6/Gen 7, and Ethernet-based connectivity products. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Principle Design Verification Engineer Serdes/Phy Astera LabsPrinciple Design Verification Engineer Serdes/PhySan Jose, CA$207,000–$230,000 / yearYou'll partner directly with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks that ship into the world's most advanced AI platforms, including UALink, UCIe, PCIe Gen 6/Gen 7, and Ethernet-based connectivity products. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.
Senior Staff PCB Layout Design Engineer D-MatrixSenior Staff PCB Layout Design EngineerSanta Clara, CAPower Delivery Optimization: Work with Power Engineers to implement complex PDN strategies, including multi-phase VRM layouts and optimized decoupling capacitor placement for high-TDP ASICs. You will own the layout of high-complexity, high-layer-count PCBAs (20+ layers), ensuring that 112G/224G SerDes signals remain pristine and that thousands of Amps are delivered across the board with minimal loss.
Technical Lead Design Verification Engineer Astera LabsTechnical Lead Design Verification EngineerSan Jose, CAAstera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Staff High Voltage Electrical Engineer, EPC Redwood Materials IncStaff High Voltage Electrical Engineer, EPCSan Francisco, CA$190,000–$252,500 / yearResponsibilities will include: Lead the design of high voltage AC electrical systems, specifically for industrial substations (69kV to 345kV) and their integration with upstream transmission lines and downstream MV distribution. Redwood is localizing a global battery supply chain that seamlessly integrates recovery, reuse, and recycling - keeping critical minerals in circulation and driving the energy transition.
NewHardware Design Engineer Super Micro Computer Spain, S.L.Hardware Design EngineerSan Jose, CADate: Jun 15, 2026Location: San Jose, California, United StatesCompany: Super Micro ComputerJob Req ID: 29120About SupermicroSupermicro® is a Top Tier provider of advanced server, storage, and networking solutions for Data Center, Cloud Computing, Enterprise IT, Hadoop/ Big Data, Hyperscale, HPC and IoT/Embedded customers worldwide. You will work closely with cross-functional engineering teams and external partners to deliver robust, competitive, and high-quality board designs.
Staff High Voltage Electrical Engineer, EPC Redwood MaterialsStaff High Voltage Electrical Engineer, EPCSan Francisco, CA$190,000–$252,500 / yearResponsibilities will include: Lead the design of high voltage AC electrical systems, specifically for industrial substations (69kV to 345kV) and their integration with upstream transmission lines and downstream MV distribution. Redwood is localizing a global battery supply chain that seamlessly integrates recovery, reuse, and recycling - keeping critical minerals in circulation and driving the energy transition.
NewSystems Design/Product Development Engineer (semiconductor/capital equipment) KLASystems Design/Product Development Engineer (semiconductor/capital equipment)Milpitas, CA$117,800–$200,300 / yearEnabling the movement towards advanced chip design, KLA's Global Products Group (GPG), which is responsible for creating all of KLA's metrology and inspection products, is looking for the best and the brightest research scientist, software engineers, application development engineers, and senior product technology process engineers. The ideal candidate will be a strong problem solver with a passion for operational excellence and cross‑functional collaboration; lead engineering development projects for mask inspection products in the RAPID division of KLA.Assess, evaluate risks, and drive projects forward with an eye for critical path.
Wireless MAC Design Engineer Apple IncWireless MAC Design EngineerSunnyvale, CACome join Apple's wireless silicon development effort, with its emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically coordinated engineering team. Develop MAC layer design for wireless communication SoCs, including creating microarchitecture and other documents based on system-level requirements, and writing area- and power-efficient RTL that is scalable.
NewAI Research Scientist- World Model Bosch Group IncAI Research Scientist- World ModelSunnyvale, CAThe Bosch Research and Technology Center North America with offices in Sunnyvale, California, Pittsburgh, Pennsylvania, and Cambridge, Massachusetts is a part of the global Bosch Group (www.bosch.com), a company with over 70 billion euro revenue, 400,000 employees worldwide, a very diverse product portfolio, and a history spanning over 125 years. Our award-winning team (IEEE VIS best paper & best paper runner-ups) actively collaborates with leading academic and industry groups to advance research ideas and disseminate findings in top AI conferences and journals, such as CVPR, ICCV, ICRA, ECCV, NeurIPS, ICLR, TVCG, SIGGRAPH.
Control Systems Engineer Lawrence Livermore National LaboratoryControl Systems EngineerLivermore, CA$146,340–$222,564 / yearFunction independently with minimal direction, taking significant responsibility and using advanced knowledge and judgment to establish objectives, prioritize parallel tasks, allocate resources, and collaborate in the development of innovative methods/technology to guide the completion of projects and contribute to the development of organizational goals. Advanced verbal and written communication skills with the ability to effectively prepare, present, and explain technical information, provide advice to senior management and external stakeholders, and collaborate with technical staff, managers, stakeholders, and vendors at all organizational levels.
Staff Product Design Engineer uraStaff Product Design EngineerSan Francisco, CaliforniaProject Experience : 10+ years of experience as a consumer product design engineer who loves working on highly creative, fast-paced, and collaborative teams alongside Industrial Designers, Hardware Engineers, and UX Designers. Driven, Technical Leadership: Able to drive tasks independently, act as a leader and mentor across multiple organizations, organize, escalate and communicate issues and needs clearly.
Senior Product Design Engineer uraSenior Product Design EngineerSan Francisco, CaliforniaProject Experience : 6+ years of experience as a consumer product design engineer who loves working on highly creative, fast-paced, and collaborative teams alongside Industrial Designers, Hardware Engineers, and UX Designers. Driven, Technical Leadership: Able to drive tasks independently, act as a leader and mentor across multiple organizations, organize, escalate and communicate issues and needs clearly.
Power Systems Design Engineer EtchedPower Systems Design EngineerSan Jose, CaliforniaAs a Power Systems Design Engineer at Etched, you will be pivotal in designing, selecting, and qualifying power supply solutions to meet extremely high power demands for processors. You will work closely with power supply vendors and leverage your expertise in multi-phase power solutions, 48V input conversion, and power loss analysis to ensure optimal performance and reliability.
Senior Hardware Design Engineer AstreyaSenior Hardware Design EngineerSunnyvale, California107,520.00 - $134,400.00 USD (Salary) Please note that the salary information provided herein is base pay only (gross); it does not include other forms of compensation which may or may not apply to this specific position, namely, performance-based bonuses, benefits-related payments, or other general incentives - none of which are guaranteed, may be subject to specific eligibility requirements, and are wholly within the discretion of Astreya to remit. Where an applicant or employee is placed on this range will depend and be contingent on objective, documented work-related considerations like education, experience, certifications, licenses, preferred qualifications, among other factors.
Sr. Asic Design Verification Engineer (Silicon Engineering) Space Exploration TechnologiesSr. Asic Design Verification Engineer (Silicon Engineering)Palo Alto, CA$175,000–$280,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Physical Design Engineer EtchedPhysical Design EngineerSan Jose, CaliforniaIn this role, youwill own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed. Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS,routing, IR drop, and EM/antenna analysis.
Sr. ASIC Design Verification Engineer (Silicon Engineering) SpaceXSr. ASIC Design Verification Engineer (Silicon Engineering)Palo Alto, CA$175,000–$280,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
Sr. RTL Design Engineer (Silicon Engineering) Space Exploration TechnologiesSr. RTL Design Engineer (Silicon Engineering)Sunnyvale, CA$175,000–$280,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). ITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
NewSenior Principal Engineer, Hardware Application Engineering – Board & System Design Bright Vision TechnologiesSenior Principal Engineer, Hardware Application Engineering – Board & System DesignSanta Clara, CA$200,000–$266,400 / yearJob Title: Senior Principal Engineer, Hardware Application Engineering – Board & System Design Location: Santa Clara, CA 100% Onsite Salary: $200,000 – $266,400 annually Job Summary We are seeking a Senior Principal Engineer to lead board and system hardware design for next-generation Ethernet switch, networking, and AI infrastructure platforms. In this customer-facing technical leadership role, you will work closely with customers and internal engineering teams to support hardware design from architecture through production, ensuring high-performance, reliable, and manufacturable solutions.
Principal Design Verification Engineer (Silicon Engineering) Space Exploration TechnologiesPrincipal Design Verification Engineer (Silicon Engineering)Palo Alto, CA$210,000–$355,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
NewHardware Design Engineer iTCO SolutionsHardware Design EngineerSan Jose, CAWe are seeking a highly skilled ASIC Design / SDC Engineer to join a world-class silicon engineering team building next-generation networking chips for high-performance, web-scale, and service provider systems. The ideal candidate is a detail-oriented engineer who enjoys solving deep timing and constraint challenges, collaborating across disciplines, and driving silicon-level correctness from block to full chip.
NewSenior Principal Board Design Engineer Bright Vision TechnologiesSenior Principal Board Design EngineerSanta Clara, CAFull timeIn this customer-facing technical leadership role, you will work closely with customers and internal engineering teams to support hardware design from architecture through production, ensuring high-performance, reliable, and manufacturable solutions. As we continue to grow, we’re looking for a skilled Senior Principal Board Design Engineer to join our dynamic team and contribute to our mission of transforming business processes through technology.
ASIC Design Hardware Engineer - SDC/STA ITCO SolutionsASIC Design Hardware Engineer - SDC/STASan Jose, CACisco s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and cafe, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Being a member of design team who develops block level and full-chip SDCs and works with physical design and DFT teams to close full-chip timing in multiple timing modes.
Product Design Engineer V || Cupertino, CA (Onsite) Pride GlobalProduct Design Engineer V || Cupertino, CA (Onsite)Cupertino, CA$4,477.60 / weekOnly applicable for San Francisco Candidates : Under the San Francisco Lactation in the Workplace Ordinance, we will provide written notice of lactation accommodation rights, and this notice will automatically be given upon hiring, any inquiry of parental leave or lactation accommodation. In this position, you will leverage your expertise in mechanics, materials, and numerical simulation methods to support the structural design and validation of innovative consumer technology products.
Mechanical Design Engineer with Creo Pyramid Consulting, IncMechanical Design Engineer with CreoSan Jose, CA$45–$50 / hourKeywords for Candidate Search-("Mechanical Design Engineer" OR "Mechanical Engineer") AND (Creo OR NX) AND ("Electronic Enclosures" OR Chassis OR Rackmount OR Networking OR Switches OR Routers OR Servers) AND ("Sheet Metal" or Sheet) AND (GD&T or "Tolerance Analysis"). By applying to our jobs you agree to receive calls, AI-generated calls, text messages, or emails from Pyramid Consulting, Inc. and its affiliates, and contracted partners.
NewSenior Cell Test & Validation Engineer Peak EnergySenior Cell Test & Validation EngineerBurlingame, CA$150,000–$170,000 / yearLead the transition from verification to validation: design statistically rigorous test campaigns (sample size justification, DOE, GR&R, capability analysis, tolerance intervals, reliability statistics) that establish confidence in production-intent cells. Build and qualify in-house test and data-acquisition fixtures — including thermal chambers, calorimetry setups, current/voltage harnesses, temperature sensing, and custom DAQ — to expand internal test capability and reduce reliance on external labs.
Staff Electrical Design Engineer, Cybercab, Next Gen Battery Electronics Tesla IncStaff Electrical Design Engineer, Cybercab, Next Gen Battery ElectronicsPalo Alto, CA$192,000–$288,000 / yearTesla's Battery Electronics team is hiring an experienced Electrical Design Engineer to lead the design of high-voltage battery management PCBAs for our newest vehicles, including the Robotaxi and next-generation mass market platforms, Roadster, Semi, Cybertruck, as well as our established SX3Y lineup, residential and industrial energy storage solutions, and Optimus. Collaborating closely with mechanical design, firmware engineering, test, and manufacturing teams, you will optimize your designs for best-in-class performance and reliability while also focusing on minimizing parts count and reducing BOM costs.
Principal RF Design Engineer 6 Kratos DefensePrincipal RF Design Engineer 6San Jose, CA$140,000–$200,000 / yearKratos Defense & Security Solutions, Inc. (NASDAQ:KTOS) develops and fields transformative, affordable technology, platforms, and systems for United States National Security related customers, allies, and commercial enterprises. Design RF & microwave amplifier assemblies, analog control circuits, power supplies and power conditioning circuitry, and some basic digital circuitry for command-&-control and fault sensing & reporting.
Electrical Engineer VoltaiElectrical EngineerMenlo Park, CaliforniaBacked by Sequoia Capital, we’re putting AI in the hands of hardware engineers in over 70% of the world’s largest semiconductor and electronics companies to have effortless control over their next-generation chip and board designs, powering the future of automotive, industrial automation, consumer electronics, IoT, and semiconductor manufacturing. About the Team Our founding team consists of IOI/IPhO olympiad medalists, Stanford professors, ex-CTO of Synopsys, and our business leadership has scaled revenue in their previous companies to over $1.5bn.
NewHardware Design Engineer supermicroHardware Design EngineerSan Jose, CAAbout SupermicroSupermicro is a Top Tier provider of advanced server, storage, and networking solutions for Data Center, Cloud Computing, Enterprise IT, Hadoop/ Big Data, Hyperscale, HPC and IoT/Embedded customers worldwide. You will work closely with cross-functional engineering teams and external partners to deliver robust, competitive, and high-quality board designs.
Robot Physics Modeling Engineer, Model Based Design, Optimus Tesla IncRobot Physics Modeling Engineer, Model Based Design, OptimusPalo Alto, CA$140,000–$300,000 / yearWelcome to Tesla's Optimus Robotics Team, the epicenter of innovation, where we're not just designing humanoid bi-pedal robots like the Tesla Bot; we're creating a revolution in automation for repetitive tasks and pioneering wheeled robots for manufacturing and autonomous logistics. Analysis skills including statics, multibody dynamics, vibration, kinematics, stress, fatigue and thermal analyses; proficency in multibody dynamics modeling and simulation of robotics systems preferred.