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Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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Astera Labs

Principal PCS/PMA RTL Design Engineer

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Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Principal Pcs/Pma RTL Design Engineer

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The ideal candidate combines deep expertise in semiconductor design flows, EDA tools, infrastructure engineering, and large-scale automation with strong leadership and cross-functional collaboration skills. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry.

Lattice Semiconductor Corp

Principal Engineer – CAD Design Engineering & EDA Infrastructure

Our "Corsair" platforms push the limits of signal density and power delivery, and you will own layout for high-complexity, high-layer-count PCBAs (20+ layers) — ensuring 112G/224G SerDes signals stay clean and thousands of amps are delivered with minimal loss. Beyond hands-on layout, you will serve as custodian of our Design Methodology, driving the automation, tooling, and constraint management processes that let hardware development scale with precision and speed.

d-Matrix

Sr. Staff PCB Design Engineer

Lattice Semiconductor Corporation

Principal Engineer - CAD Design Engineering & EDA Infrastructure

Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.

Sr. Staff Design Engineer

Power- and timing-aware design — managing block activity, clock-gating, pipelining, and retiming; partner with the backend team on physical closure for your blocks. You design and implement the digital front-end RTL at the heart of the chip — including the high-speed datapath that moves data between UCIe and the optical front end.

Lumilens

IC/RTL Design Engineer

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Engineers in this role may work on different aspects of Physical Design ASIC and SoC development, including floorplan, Clock Tree Synthesis, low power implementation, timing analysis, design methodology, automation and enabling new technology nodes. This is an excellent opportunity to join a fast-paced engineering team developing leading-edge products on advanced process technologies while collaborating with world-class design, verification, implementation, and physical design teams.

Qualcomm Inc

Physical Design Engineer

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You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.

Cerebras Systems

Lead RTL Design Engineer

Working closely with product design engineers, you'll perform PCB layout of high speed/high-density value-conscious PCBs for all business units at NVIDIA (Information Network, GPU Desktop, Notebook, Automotive, Professional, Data Center, Deep Learning, and AI). We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our exclusive engineering teams are rapidly growing.

Visualize your future . . . We Do 
NVIDIA is the world leader in graphics processing technologies, creating innovative, industry-changing products for computing, consumer electronics, and mobile devices. NVIDIA products are transforming visually-rich applications such as video games, film production, broadcasting, industrial design, space exploration, and medical imaging. We invest in our people and our technologies, support and fund industry research around the world, and consistently deliver high-quality products. NVIDIA's culture promotes and inspires a team of world-class employees to be at the top of their game. We've created an environment where talents are recognized and collaboration is valued. Our employees are shaping the world of tomorrow. . . today. We invite you to explore the opportunities available at NVIDIA to see what your future may hold.

NVIDIA

PCB Design Layout Engineer

Large language models, coding agents, and agentic AI are transforming how chips get designed, and this role puts you at the frontier — applying the latest and greatest AI to NVIDIA's real ASIC design flows and pushing past the limits of what's currently possible. Domain and technical expertise in front-end ASIC (design, verification, timing) combined with project experience applying agentic AI to chip design and optimization problems, with a track record of driving ideas from conception through experimentation to production.

Applied Research Engineer, Chip Design

High-quality, high-performance Verilog/SystemVerilog RTL implementation based on a design specification - may also include areas such as asynchronous clock domain crossings, multiple power domains, low-power design, complex algorithms, deep computations and pipelining, multi-threaded designs, and integrating third-party IP. Working with cross functional teams such as Verification Engineering, Software/Firmware Engineering, Emulation Engineering, and Validation Engineering to support any issues that may arise on the RTL design.

Broadcom Corporation

RTL IC Design Engineer

Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.

Nvidia

Asic Design Engineer - Clocks IP

This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What you will be doing: Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.

Senior Asic Floorplan Design Engineer

This position involves working with the latest technology to continue driving next generation AI/ML ecosystems through our PCIe Switch Products - and managing mega datacenters, while leading world class performance, through our Enterprise Storage Products. As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.

IC Design Engineer

As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software, DFT, and more. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.

Senior SOC Design Engineer

This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. Collaborate and coordinate with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks.

ASIC Design Engineer - New College Grad 2026

Our work opens up new universes to explore, enables amazing creativity and discovery and powers what were once science fiction inventions from artificial intelligence to autonomous cars. Widely considered to be one of the technology world’s most desirable employers, NVIDIA is an industry leader with groundbreaking developments in High-Performance Computing, Artificial Intelligence and Visualization.

Lead Hardware Design Validation Engineer - Memory Subsystem

This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. If you love solving complex signal integrity challenges and thrive on bridging the gap between design intent and manufacturing reality, we want to hear from you.

Signal Integrity and PCB Design Engineer

This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.

Circuit Design Engineer Jobs in California

Principal PCS/PMA RTL Design Engineer Astera Labs

Principal Pcs/Pma RTL Design Engineer Astera Labs

Principal Engineer – CAD Design Engineering & EDA Infrastructure Lattice Semiconductor Corp

Sr. Staff PCB Design Engineer d-Matrix

Principal Engineer - CAD Design Engineering & EDA Infrastructure Lattice Semiconductor Corporation

Sr. Staff Design Engineer Lattice Semiconductor Corp

IC/RTL Design Engineer Lumilens

Physical Design Engineer Qualcomm Inc

Lead RTL Design Engineer Cerebras Systems

PCB Design Layout Engineer NVIDIA

Applied Research Engineer, Chip Design NVIDIA

RTL IC Design Engineer Broadcom Corporation

Asic Design Engineer - Clocks IP Nvidia

Senior Asic Floorplan Design Engineer Nvidia

IC Design Engineer Broadcom Corporation

Senior SOC Design Engineer Nvidia

ASIC Design Engineer - New College Grad 2026 NVIDIA

Lead Hardware Design Validation Engineer - Memory Subsystem NVIDIA

Signal Integrity and PCB Design Engineer NVIDIA

ASIC Floorplan Design Engineer - New College Grad 2026 NVIDIA

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