Design verification engineer RD solutionsDesign verification engineerSan Jose, CAFull timemost critical and large-scale challenges across the aerospace & defense, automotive, energy, hi-tech, healthcare, medical devices, rail and semiconductor industries. meaningful work and be part of an organization that truly believes when you win, we all win, and when you fail, we all learn, then we’re eager to hear from you.
Verification Engineer III (Prototype) BC ForwardVerification Engineer III (Prototype)Sunnyvale, CAFull timeThe ideal candidate will have strong experience in electrical system-level verification, test infrastructure development, and test automation and a proven ability to define verification requirements, execute comprehensive test plans, and communicate results to stakeholders . With delivery centers and offices across North America and India, we take pride in building long-term relationships and delivering excellence through innovation, collaboration, and integrity.
NewMechanical Design Engineer - Commercial HVAC JobotMechanical Design Engineer - Commercial HVACAlameda, CA$55–$75 / hourInformation collected and processed as part of your Jobot candidate profile, and any job applications, resumes, or other information you choose to submit is subject to Jobot's Privacy Policy, as well as the Jobot California Worker Privacy Notice and Jobot Notice Regarding Automated Employment Decision Tools which are available at jobot.com/legal. Field Integration: Provide support during construction with activities like submittal reviews, resolving RFIs, and participating in site assessments to ensure smooth project execution.
NewRailway Engineer - Remote Teoresi GroupRailway Engineer - RemoteSan Francisco, CARemoteIntegration of onboard and wayside subsystems, including signaling components, sensors, communication interfaces, and control units, into system-level testing environments (e.g., HIL/SIL). At Teoresi, we specialize in supporting companies in creating projects using cutting-edge technologies such as self-driving cars and nanotechnology for the medical field.
Physical Design Engineer Einfochips (An Arrow electronics company)Physical Design EngineerSan Jose, CA$110,000–$130,000 / yearContractorFull timeContribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC). Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
Enterprise Sales Engineer - Sales Engineering PlaidEnterprise Sales Engineer - Sales EngineeringSan Francisco, CA$196,800–$322,800 / yearWe work with thousands of companies like Venmo, SoFi, several of the Fortune 500, and many of the largest banks to make it easy for people to connect their financial accounts to the apps and services they want to use. You will ensure a successful transition to the post-sale stage of the customer lifecycle and partner with account teams to drive adoption of new products by existing customers.
Design Verification Engineer Silicon Engineering Space Exploration Technologies CorpDesign Verification Engineer Silicon EngineeringPalo Alto, CA$135,000–$155,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
NewSenior Design Verification Engineer Hewlett Packard EnterpriseSenior Design Verification EngineerSunnyvale, CaliforniaPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.
NewFPGA Design & Verification Engineer (UVM)– (Hybrid – Sunnyvale, CA) Stage 4 Solutions IncFPGA Design & Verification Engineer (UVM)– (Hybrid – Sunnyvale, CA)Sunnyvale, CA$100–$125In this role, you will design, verify, and integrate ASIC/FPGA solutions for high-speed digital and DSP applications using UVM-based verification methodologies, while supporting System-on-Chip (SoC) development, FPGA platforms, automation scripting, and cross-functional collaboration to deliver complex, high-performance systems. Cross discipline collaboration with Systems Architects, RF/Analog & Digital Circuit designers and ASIC/FPGA engineers to create leading edge products for future business growth, contributing to complex systems employing high speed networking concepts.
Principal Design Verification Engineer Silicon Engineering Space Exploration Technologies CorpPrincipal Design Verification Engineer Silicon EngineeringSunnyvale, CA$210,000–$310,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Sr. ASIC Design Verification Engineer Silicon Engineering Space Exploration Technologies CorpSr. ASIC Design Verification Engineer Silicon EngineeringPalo Alto, CA$175,000–$280,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Design Verification Engineer BaiduDesign Verification EngineerSunnyvale, CaliforniaYou will help on UVM Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development. Work closely with the design and systems engineering teams to review specifications and architecture, extract features, define verification plan & coverage model.
NewSenior ASIC Design Verification Engineer, Silicon Google LLCSenior ASIC Design Verification Engineer, SiliconMountain View, CAAct as a key liaison, interacting with multiple subsystem design and verification leads to understand unique requirements, engage in architectural discussions, and provide customizable verification solutions that bridge different subsystems. Create and execute scalable testplans and coverage models designed to track, manage, and close requirements across multiple versions and iterations of the design.
ASIC Formal Verification Engineer, TPU Compute Google LLCASIC Formal Verification Engineer, TPU ComputeSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing with key teams working on the development of our TPUs Vertex AI for Google Cloud Google Global Networking Data Center operations systems research and much more. Careers Skip navigation links home Home work_outlinework_outline Jobs noogler_hat Students google How we work handyman How we hire person_outline Your career help_outline Help link feedback Send feedback more_vert Help Send Feedback Sign in.
Verification Engineer - Aeromechanical (Design & Test) PivotalVerification Engineer - Aeromechanical (Design & Test)Palo Alto, CaliforniaDemonstrates a proactive safety mindset by embedding safety into daily operations, identifying and mitigating risks through assessments and training, encouraging open dialogue on safety concerns, and continuously improving protocols to ensure a safe work environment. Actively seeks and values diverse stakeholder perspectives, builds cross-functional relationships, and fosters trust through empathetic, fact-based communication—committing to shared decisions for the greater good.
Digital - Principal Digital Verification Engineer Eliyan CorporationDigital - Principal Digital Verification EngineerCAAs an Eliyan Principal Digital Verification Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be a key technical leader in developing state-of-the-art testbenches and unit/chip level test cases for best-in-class PHYs and Controllers.
Multimedia Design Verification Engineer, Silicon Google LLCMultimedia Design Verification Engineer, SiliconMountain View, CAPlan the verification of multimedia design blocks at subsystem level by understanding the design specification, and interacting with architecture and design engineers to identify important verification scenarios. Work with designers, architects, and other stakeholders to come up with detailed test plans, dependencies, and deliverables, while representing DV status throughout the development process.
ASIC Design Verification Engineer, TPU Compute Google LLCASIC Design Verification Engineer, TPU ComputeSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
ASIC Design Verification Engineer, Platforms and Devices Google LLCASIC Design Verification Engineer, Platforms and DevicesMountain View, CAExperience with architectural background in one or more of the following: caches hierarchies, coherency, memory consistency models, DDR/LPDDR, PCIe, packet processors, security, clock, and power controllers. You will also work on developing high performance VIPs for protocols supported by our SOCs and closely collaborate on the deployment of the verification stack across a heterogeneous set of IPs.
Design Verification Engineer, TPU Cloud Compute Google LLCDesign Verification Engineer, TPU Cloud ComputeSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
CPU Design Verification Engineer Google LLCCPU Design Verification EngineerMountain View, CAGoogle is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. Minimum qualifications: Bachelor"s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
Sr. Design Verification Engineer Credo Semiconductor, Inc.Sr. Design Verification EngineerSan Jose, CA$130,000–$160,000 / yearOur product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. You'll develop and execute verification plans, build scalable reusable testbenches, write SV-UVM sequences, debug issues, and collaborate closely with RTL designers and firmware/application engineering teams.
Senior Design Verification Engineer Google LLCSenior Design Verification EngineerMountain View, CAApplyshare linkCopy linkemailEmail a friendMinimum qualificationsBachelors degree in Electrical Engineering Computer Engineering Computer Science a related field or equivalent practical experience.8 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience with different verification techniques and methodologies including formal GLS UPF based Power simulations UVM and C based testing etc. to achieve bug-free Silicon in complex SoCs.
Design verification Engineer ApolisDesign verification EngineerSan Jose, CA$65–$70 / hourA bachelor’s degree in electrical or computer engineering, accompanied by a minimum of 8 years of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline. Key Skill: SV/UVM, AXI expertise, NOC/Crossbar, Performance.
CPU Processor Performance Verification Engineer Apple IncCPU Processor Performance Verification EngineerSanta Clara, CAWork closely with OS and compiler teams on system and application performance tuningMinimum BS and 3+ years of relevant industry experience Performance modeling, processor verification, or RTL design experience Experience in digital logic design, CPU architecture, and microarchitecture Experience in developing performance test plans and writing/debugging assembly tests for performance correlation and verification Programming skills in assembly, C/C++, Verilog, System Verilog, or scriptingExperience in benchmark and workload analysis and CPU performance profiling Knowledge of compiler techniques and OS for performance optimization Knowledge in developing instruction profiling tools on silicon Experience in performance modeling for advanced CPU designs Experience in silicon validation Ability to work across teams to optimize silicon performance Should be a great teammate with excellent communication and presentation skills and able to work independently on the owned unit. As a CPU Processor Performance Verification Engineer owning the verification of a certain area of performance features in a chip design, you will have responsibilities as follows: Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon).
NewPrincipal Design Verification Engineer Bright Vision TechnologiesPrincipal Design Verification EngineerSanta Clara, CAFull timeBright Vision Technologies is a forward-thinking software development company dedicated to building innovative solutions that help businesses automate and optimize their operations. As we continue to grow, we’re looking for a skilled Principal Design Verification Engineer to join our dynamic team and contribute to our mission of transforming business processes through technology.
Sr. Full Chip Physical Verification Engineer Silicon Engineering Space Exploration Technologies CorpSr. Full Chip Physical Verification Engineer Silicon EngineeringSunnyvale, CA$175,000–$280,000 / yearPREFERRED SKILLS AND EXPERIENCE: Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation). We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Staff ASIC Design Verification Engineer Google LLCStaff ASIC Design Verification EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing with key teams working on the development of our TPUs Vertex AI for Google Cloud Google Global Networking Data Center operations systems research and much more. Were the driving force behind Googles groundbreaking innovations empowering the development of our cutting-edge AI models delivering unparalleled computing power to global services and providing the essential platforms that enable developers to build the future.
Senior Design Verification Engineer, Multimedia/AI/ML, Silicon Google LLCSenior Design Verification Engineer, Multimedia/AI/ML, SiliconMountain View, CAPlan the verification of multimedia design blocks at subsystem level by understanding the design specification, and interacting with architecture and design engineers to identify important verification scenarios. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement.
NewSenior Design Verification Engineer, Silicon Google LLCSenior Design Verification Engineer, SiliconMountain View, CAExecute gate-level simulations (GLS) and Unified Power Format (UPF)-based power simulations, performing debugging to deliver high-performance and low-power hardware. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement.
FPGA Design/Verification Engineer The Structures Company, LLCFPGA Design/Verification EngineerSunnyvale, CAAs trusted partners to major aerospace OEMs and Tier 1 suppliers, we connect professionals with opportunities to grow and excel in the aviation and aerospace industries. The Structures Company is a premier national aerospace and defense staffing agency specializing in contract, contract-to-hire, and direct hire placements.
ASIC Design Verification Engineer (Santa Clara, CA) Qualcomm IncASIC Design Verification Engineer (Santa Clara, CA)Santa Clara, CA$126,700–$190,100 / yearThe responsibility of the position involves comprehensive pre-silicon test planning for digital power IP''s, its testbench development using the advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model development and formal verification (property checking). General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives.
Integration and Verification Engineer, Turbogenerator Archer Aviation IncIntegration and Verification Engineer, TurbogeneratorSan Jose, CA$172,000–$216,000 / yearOur sights are set high and our problems are hard, and we believe that diversity in the workplace is what makes us smarter, drives better insights, and will ultimately lift us all to success. Archer is an aerospace company based in San Jose, California building an all-electric vertical takeoff and landing aircraft with a mission to advance the benefits of sustainable air mobility.
Sr. Staff ASIC Verification Engineer Rivian Automotive IncSr. Staff ASIC Verification EngineerPalo Alto, CA$237,000–$296,000 / yearRivian may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law. Rivian may share your Candidate Personal Data with (i) internal personnel who have a need to know such information in order to perform their duties, including individuals on our People Team, Finance, Legal, and the team(s) with the position(s) for which you are applying; (ii) Rivian affiliates; and (iii) Rivian's service providers, including providers of background checks, staffing services, and cloud services.
CPU DFT Verification Engineer Apple IncCPU DFT Verification EngineerSanta Clara, CAWork with the silicon bringup team on developing tests that help the silicon bring up effortMinimum BS and 3+ years of relevant industry experience Experience in DFT design, DFT verification, or processor verification Experience with digital logic design, test/debug feature, or DFT architecture Experience with DFT and structural debug concepts and methodologies: JTAG, IEEE1500, or MBIST and scan Experience in scripting in Python, Perl, or TCLMaster's degree preferred Understanding of CPU architecture Experience in developing design verification test plans, test benches, and test vectors generation Experience with lab debug of CPUs/ASIC using built-in DFT and debug features is a plus In-depth knowledge in design verification environments like random constraint verification Knowledge of Verilog and experience with simulators and waveform debugging tools Should be an extraordinary teammate with excellent communication skills with the ability to articulate complex design issues during verification effort Be able to create and follow detailed work schedule and work independently on the verification efforts for a block/area of the design. In this highly visible role, you will be at the center of a chip design effort collaborating with all subject areas, with a critical impact on getting functional products to millions of customers quickly.
NewASIC verification engineer Hewlett Packard EnterpriseASIC verification engineerSunnyvale, CaliforniaProvide technical expertise and leads project teams of Electronic and VLSI engineers and internal and outsourced development partners responsible for all stages of VLSI design and development for complex products, solutions, and platforms, including design, validation, and testing. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.
WiFi MAC Design Verification Engineer Apple IncWiFi MAC Design Verification EngineerSunnyvale, CAAs a Wireless MAC Design Verification Engineer, you'll be instrumental in our WCS group's verification initiatives, ensuring that our products incorporate cutting-edge Wi-Fi technology while maintaining high quality and reliability. By leveraging cutting-edge processes, tools, workflows, unique proprietary features, and advanced architecture, the team strives to provide the best wireless connectivity solutions.
Verification Engineer Advanced Micro Devices IncVerification EngineerSan Jose, CAAs a member of the front-end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first pass silicon success. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives.
IP Verification Engineer Advanced Micro Devices IncIP Verification EngineerSan Jose, CAProficient in IP level ASIC verification • Expert in Verilog, System Verilog, Object Oriented programming • Expert in developing UVM based verification frameworks and testbenches • Scripting and automation of verification processes and flows • Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process • Good Computer Architecture, systems knowledge • Comfortable in python / perl and editing / maintaining scripts • Exposure to leadership or mentorship is an asset • Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out • Experience with PCIe, CXL, NVMe or ethernet protocols • Strong communication skills and the ability to work independently as well as in a cross-site team environment. • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified • Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases • Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers • Build the directed and random verification tests • Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality.
CPU Top-Level Design Verification Engineer Apple IncCPU Top-Level Design Verification EngineerSanta Clara, CADevelop coverage monitors and analyze coverage to ensure all the test cases in the plans are coveredMinimum BSBS in Electrical Engineering, Computer Science, or Computer Engineering preferred Computer Architecture - Strong understanding of processor design, instruction set architectures, pipeline design, cache hierarchies, and memory systems RTL development - Experience creating efficient, synthesizable RTL code with understanding of timing closure, area optimization, and power-aware design techniques SystemVerilog - Proficiency in SystemVerilog including advanced features like interfaces, assertions, and verification constructs. As a CPU Top-Level Design Verification Engineer owning the verification methodology, tools, and flow of a high performance lower power processor design, you will have the responsibilities as follows: Work closely with verification engineers and RTL designers on defining effective verification methodology for low power complex processor design.
Lead SoC Verification Engineer AnodizeLead SoC Verification EngineerLos Altos, CaliforniaWe’re a well-funded, stealth startup building a next-generation, end-to-end computing platform powered by a custom, high-performance edge SoC on an advanced process node. We’re building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process.
Senior Digital Verification Engineer Ethan Alexander GroupSenior Digital Verification EngineerSan Francisco, CaliforniaKnowledgeable of common DV techniques such as assertions, SV, OVM/UVM, constrained random, and coverage (code/functional/assertion). We're is looking for a digital verification engineer who is passionate about delivering differentiated low-power and battery-free wireless connectivity solutions.
Design Verification Engineer - Physical AI Compute Velaura AI IncDesign Verification Engineer - Physical AI ComputeSunnyvale, CA
Senior Design Verification Engineer - Physical AI Compute Velaura AI IncSenior Design Verification Engineer - Physical AI ComputeMenlo Park, CA
Senior Design Verification Engineer Pyramid Consulting, IncSenior Design Verification EngineerSan Jose, CA$150,000–$160,000 / yearAnalyze and debug simulation failures at the RTL and gate-level , including working with gate-level netlists and SDF timing simulations. By applying to our jobs you agree to receive calls, AI-generated calls, text messages, or emails from Pyramid Consulting, Inc. and its affiliates, and contracted partners.
NewSoC Verification Engineer Intel CorpSoC Verification EngineerSanta Clara, CA$141,910–$200,340 / yearBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 4+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning. Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 3+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning.
Sr. Staff ASIC Verification Engineer Recogni IncSr. Staff ASIC Verification EngineerSunnyvale, CAResponsibilities: Your responsibilities will be wide-ranging and and run the gamut of working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular SystemVerilog and UVM, handling bug tracking and coverage convergence and developing scripts and methodologies for the front-end ASIC flow. This ASIC's design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to deliver the high-performance multi-chip silicon solutions that are at the heart of Tensordyne's vertically integrated, generative AI inference acceleration systems for data centers.
IP Design Verification Engineer Intel CorpIP Design Verification EngineerSanta Clara, CA$141,910–$200,340 / yearBusiness group: The Central Engineering Group (CEG) is Intel''s data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel''s product and foundry businesses.
Platform Verification Engineer - Embedded Systems WaabiPlatform Verification Engineer - Embedded SystemsSan Francisco, CA$133,650–$222,000 / yearWith offices in Toronto, San Francisco, Dallas, and Pittsburgh, Waabi is growing quickly and looking for diverse, innovative and collaborative candidates who want to impact the world in a positive way. We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information.
Sr. ASIC Verification Engineer Recogni IncSr. ASIC Verification EngineerSunnyvale, CAResponsibilities: Your responsibilities will be wide-ranging and and run the gamut of working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular SystemVerilog and UVM, handling bug tracking and coverage convergence and developing scripts and methodologies for the front-end ASIC flow. This ASIC's design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to deliver the high-performance multi-chip silicon solutions that are at the heart of Tensordyne's vertically integrated, generative AI inference acceleration systems for data centers.