li>Required to research, design, write, and review a wide range of technical documentation that will include but not be limited to: technical manuals, design specification documents, interface requirements specification, system user guides, reference manuals, installation guides, and data sheets that may be required to assist with the design, integration, testing, and fielding of the system; will provide project briefing materials upon request. June 4, 2026
For U.S. Positions: While subject to change based on business needs, Leidos reasonably anticipates that this job requisition will remain open for at least 3 days with an anticipated close date of no earlier than 3 days after the original posting date as listed above.
The Senior Test Engineer is responsible for the development and execution of Acceptance Test Procedures (ATP), Manufacturing Test Procedures (MTP), Qualification Test Procedures (QTP), designing and building test equipment and writing Equipment Operating Instructions (EOI). This position is accountable for ensuring that the testing of products meets all customer specifications and that the test equipment is available in a timely manner.
May 19, 2026For U.S. Positions: While subject to change based on business needs, Leidos reasonably anticipates that this job requisition will remain open for at least 3 days with an anticipated close date of no earlier than 3 days after the original posting date as listed above. If you received an email purporting to be from Leidos that asks for payment-related information or any other personal information (e.g., about you or your previous employer), and you are concerned about its legitimacy, please make us aware immediately by emailing us at LeidosCareersFraud@leidos.com.
ITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
p>ITAR REQUIREMENTS: - To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
p>ITAR REQUIREMENTS: - To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Huntington Beach, CA30+ days ago
p>• Develop FPGA/ASIC designs supporting design and/or verification teams • Implement FPGA/ASIC with latest design practices and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs) • Integrate DSP IP from Boeing's algorithm team and third-party IP as needed • Perform static timing analysis, LEC, CDC, linting, and other necessary checks to ensure the design is completed on schedule • Develop Functional Coverage Models and perform Code Coverage to verify designs in simulation • Create self-checking and reusable test benches from scratch, applying Object Oriented Programming concepts such as Inheritance and Polymorphism, and leverage UVM to build agents consisting of drivers, sequencers, monitors, and use of predictors together with scoreboards for checking correctness. • Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement • Experience with ASIC/FPGA design or verification • Experience with ASIC/FPGA architectural definition, and detailed design implementation and functional verification using SystemVerilog with delivery/release of production designs • Experience with hardware-based integration and test of ASIC/FPGA designs.
Huntington Beach, CA7 days ago
p>From complex digitally beamformed phased arrays for constellation satellite programs to computing and networking equipment for commercial airplanes, the Boeing Electronic Products group develops ASICs and FPGAs that are at the heart of Boeing's products! Our diverse development portfolio provides opportunities to learn with exposure to the breadth of the Boeing product line - approximately half our design work is within the Space & Launch business unit, and half is from other parts of Boeing (AvionX; Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems).
Huntington Beach, CA30+ days ago
p>Typical Education/Experience: Associate, Level 2: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Experienced, Level 3: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g.
Huntington Beach, CA30+ days ago
Typical Education/Experience: Experienced, Level 3: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Lead, Level 4: Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g.
p>Broadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and embedded IP, is looking for an experienced verification engineer that will be responsible for modeling and verification activities related to complex digital and mixed signal (MXS) IP blocks used in Broadcom's ASIC developments. Education and Experience required:
- BS in Electrical Engineering / Computer Engineering and 8+ years of related experience or an MS in Electrical Engineering / Computer Engineering and 6+ years of related experience.
Study design specification and create test plan Develop infrastructure in SystemVerilog/UVM to stress the design Develop and fix failures from regressions, close bugs Use LLMs to do verification efficientlyMinimum requirement of a bachelors degreeBS degree in technical subject area and a minimum 3 years relevant industry experience or equivalent strongly preferred. In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment.
All of which is driven by a world-class vertically integrated engineering team, spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW engineering. You will interact with the analog/RF design team, digital DV team digital design team, and wireless system team to develop best-in-class verification methodologies that ensure silicon-correct functionality with optimal coverage and time-to-tapeout trade-off.
Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in-class UVM Testbenches, implement effective coverage driven and directed test cases, deploy new AI tools, and implement methodologies to improve quality of tape-out readiness. This position comes with responsibility for pre-silicon RTL verification of block and top-level SOC, all aspects of SOC Design Verification engineering, and will enable you to thrive in a dynamic multi-functional organization, debate ideas openly, and deliver on complex Wireless protocol chip requirements.
p>The Digital Verification Engineer will work closely with design teams to validate digital circuit implementations, develop test benches, perform functional verification preparing Manufacturing/tester patterns and debug of failing tests. xa0 xa0 xa0 xa0 xa0 xa0 xa0(For more details on TSMC's Core Values, please visithttps://www.tsmc.com/english/aboutTSMC/values).
Costa Mesa, CA20 days ago
p>To ensure your safety and help you navigate your job search with confidence, please keep the following critical points in mind: No Financial Requests: Anduril will never solicit payment or demand personal financial details (such as banking information, credit card numbers, or social security numbers) at any stage of our hiring process. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.
PREFERRED SKILLS AND EXPERIENCE: Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation). We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market.
and/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing (CDL drivers only), vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training. Required for Certain Job Profiles: Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10,001 lbs.
and/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing (CDL drivers only), vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training. Required for Certain Job Profiles: Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10,001 lbs.
Costa Mesa, CA30+ days ago
p>To ensure your safety and help you navigate your job search with confidence, please keep the following critical points in mind: No Financial Requests: Anduril will never solicit payment or demand personal financial details (such as banking information, credit card numbers, or social security numbers) at any stage of our hiring process. You will lead verification strategy and methodology for FPGA/SoC designs on AMD (Xilinx) platforms for flight-critical avionics, owning UVM-based methodology, coverage-driven verification, and the roadmap for verification tooling across our programs.
Costa Mesa, CA22 days ago
div>California Pay Range
$70—$78 USD
Goken is committed to fostering a respectful, inclusive, and engaging workplace across all global locations.
Headquartered in Dublin, Ohio (USA) with Engineering Centers in Pune, India and Yokohama, Japan, Goken is a global Engineering Services and Product Development company founded in 2004.
As part of the COE, you will design, verify, and deliver IP subsystem building blocks powering Marvell''s most advanced custom chips for hyperscale cloud, AI, and data center customers - working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
p>Your key responsibilities will include but not be limited to: - Perform end-to-end analog/mixed-signal verification of RF Front End Modules (FEM), from block-level through full-chip integration, leveraging schematic, behavioral, and functional views to achieve comprehensive coverage while meeting project schedules. In this role, you will play a critical part in developing and advancing industry-leading AMS verification methodologies, defining scalable workflows, and selecting best-in-class tools to enable zero-defect product development while meeting competitive project schedules.
Your key responsibilities will include but not be limited to: Perform end-to-end analog/mixed-signal verification of RF Front End Modules (FEM), from block-level through full-chip integration, leveraging schematic, behavioral, and functional views to achieve comprehensive coverage while meeting project schedules. In this role, you will play a critical part in developing and advancing industry-leading AMS verification methodologies, defining scalable workflows, and selecting best-in-class tools to enable zero-defect product development while meeting competitive project schedules.
The SoC family of multi-core CPU processors and Radio Access SoCs offer best-in-class performance, low power, rich software ecosystem, virtualization features, and open source application support with highly optimized custom ARM CPU cores providing an excellent solution for a highly flexible end-to-end optimized 5G platform. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
Long Beach, California19 days ago
p>JetZero is seeking an experienced Flight Control Laws Validation & Verification (V&V) Engineer to support the development, verification, and validation of advanced flight control laws for the BWB Demonstrator. This is only going to increase: Air travel is forecasted to double by 2050, while meaningful efficiency gains using current airplanes have hit a wall.
and/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing (CDL drivers only), vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training. Required for Certain Job Profiles: Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10,001 lbs.
p>• BS/MS/PhD or equivalent experience in CS/CE/EE • 12+ years in ASIC verification with 8+ years focused on formal verification methods • Mastery of SystemVerilog Assertions (SVA) and formal property verification • Proficient on at least one popular formal verification tool in the industry (JapserGold, VC Formal, etc.) • Good scripting skills for flow automation (tcl, python, etc.) • Good written and oral communication skills • Keen attention to details. You will employ sophisticated formal techniques to acquire sufficiently bounded proofs while working with architects, designers, and pre- & post-silicon verification teams to accomplish your tasks, as well as improve formal verification methodologies and flows.
li>Collaborating closely with architecture and RTL teams to specify properties, resolve complex issues in building, and influence micro-architecture decisions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.
You will also be eligible for equity and benefits.
Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers' specifications whether they're a major telecom organization or automotive company, etc.
p>What we need to see: • Bachelors Degree in EE, CS or CE (or equivalent experience) and 8+ years of relevant industry experience • Background with building block and SoC level testbench utilizing strong debugging and analytical skills • Experience in verification using random stimulus along with functional coverage, assertion-based verification methodologies and tools • Expertise in SystemVerilog and Universal Verification Methodology (UVM) • Experience with design and verification tools (VCS, Verdi or equivalent) • Background in UPF power verification is a plus • Experience in netlist and DFT verification is a plus • Perl/Python and C/C++ programming language experience desirable • Knowledge of ASIC design flow, from specification to GDS • Knowledge of applying machine learning to ASIC verification flow.
What youll be doing:
• As a key member of our ASIC Verification team, you will verify the design and implementation of inference accelerator • You will be responsible for verification of the ASIC design, architecture, reference models and micro-architecture using advanced verification methodologies • Understand the design and implementation of your unit, define the verification scope, develop the verification infrastructure and verify the correctness of the design • Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks • Implement and optimize automated verification flows to improve productivity and efficiency • Stay updated on the latest trends and advancements in ASIC design verification and incorporate innovative techniques into the verification process.
p>We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.
The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies. The Role:
Be part of Amazon Leo's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways.
Irvine, California30+ days ago
What You Bring: Bachelor’s or Master’s degree in Robotics, Electrical Engineering, Computer Engineering, Computer Science, Mechanical Engineering, or a related technical field.
FieldAI’s Irvine team is where embodied AI meets real robots, real sensors, and real field deployments.
Costa Mesa, CA30+ days ago
p>To ensure your safety and help you navigate your job search with confidence, please keep the following critical points in mind: No Financial Requests: Anduril will never solicit payment or demand personal financial details (such as banking information, credit card numbers, or social security numbers) at any stage of our hiring process. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.
We bring deep experience from organizations such as DeepMind, NASA JPL, Boston Dynamics, NVIDIA, Amazon, Tesla Autopilot, Cruise, Zoox, Toyota Research Institute, and SpaceX, along with a track record of field deployments and strong performance in DARPA challenge segments. We go beyond typical data-driven approaches or pure transformer-only architectures, combining rigorous engineering with learning systems proven in globally deployed solutions that deliver results today and get better every time our robots run in the field.
Costa Mesa, CA30+ days ago
p>To ensure your safety and help you navigate your job search with confidence, please keep the following critical points in mind: No Financial Requests: Anduril will never solicit payment or demand personal financial details (such as banking information, credit card numbers, or social security numbers) at any stage of our hiring process. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.
Crown Technical Systems, a Flex Company, is a leader in power distribution and protection systems concentrating on sophisticated, state-of-the-art relay and control panels, medium voltage switchgear, and enclosures (power/control buildings/ E-Houses). • Generate and maintain: Test protocols, Verification matrices, Validation reports, Engineering change documentation Generate and maintain: Test protocols, Verification matrices, Validation reports, Engineering change documentation.
Understand System Requirements and develop System Test Cases and Test Scripts using any script languages. - Requirement management tool DOORs and configuration management tools Integrity(MKS).
Our innovative approaches have resulted in the company's products being first to market in many of key areas, developing the most advanced chips and subsystems solutions to address the ever-increasing demand of higher data rates driven by video-on demand, gaming and other real time data streams. Group Description The Optical PHY (CE-OPHY) team designs ultra high-speed and optical transceivers for communication infrastructure in long-haul, metro and datacenter.
Huntington Beach, California6 days ago
The DVV will provide technical direction, guidance and support for engineering initiatives, staff, vendors, and external consultants, with a focus on directing the verification and validation (V&V) activities of the implantable components of the BiVACOR Total Artificial Heart (TAH). The DVV will monitor metrics within the development to identify potential issues and concerns with performance, scalability and quality, and work with the team to devise plans so that the teams can tactically address problems in a timely and effective fashion.