Key ResponsibilitiesDefine end-to-end verification strategy from block-level through full-chip simulation to emulation and prototypingOwn UVM-based methodology, including constrained-random, coverage-driven closure, assertions, and formal verification adoptionDrive emulation platform strategy - platform selection, capacity planning, compilation flows, and multi-project schedulingEnable system-level validation on emulation - processor boot, OS bring-up, firmware execution, and IO exercisingDeliver pre-silicon platforms for early software development in partnership with firmware and software teamsEstablish hybrid simulation-emulation methodologies using transactor-based interfaces to maximize both environmentsOwn functional coverage models and sign-off criteria, driving closure across simulation and emulation combinedLead debug and root cause analysis across simulation and emulation, driving cross-functional bug resolutionManage verification dashboards, bug tracking, and regression health to provide clear visibility to program leadershipBuild, mentor, and scale a high-performing team of verification and emulation engineersDrive verification schedules and risk mitigation aligned with chip program milestones and tapeout readinessRepresent verification and emulation in tapeout readiness reviews and program-level decision forumsCollaborate cross-functionally with Compiler Team, RTL design, architecture, DFT, physical design, and post-silicon teamsManage emulation lab infrastructure, including hardware resources, licensing, and vendor relationshipsEvaluate and adopt new EDA tools and methodologies, including AI/ML-assisted verification techniques. This role combines deep technical expertise with strong people leadership and program execution skills, and is ideal for someone who thrives at the intersection of architecture, verification methodology, hardware-software integration, and team building.