div>Our compensation reflects the cost of labor across several U.S. geographic markets, and we pay differently based on those defined markets.
- BS in Electrical Engineering or a related field plus minimum 4 years of industry experience in analog and/or mixed-signal circuit design (or MS plus minimum 2 years of industry experience).
Mountain View, CA30+ days ago
The company invented the world's first 3D-stacked photonics engine, Passage, capable of connecting thousands to millions of processors at the speed of light in extreme-scale data centers for the most advanced AI and HPC workloads. We are hiring a Mixed-Signal Digital Architecture Validation Engineer to partner with the internal engineering team at Lightmatter to deliver groundbreaking products to market.
Santa Clara, CA30+ days ago
p>Business group: The Central Engineering Group (CEG) is Intels data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). Position Overview The Aerospace, Defense & Government (ADG) Senior Analog/Mixed Signal Application Engineer specializing in Analog Mixed-Signal Design provides critical technical support to Intel Foundry Services customers on PDKs, design methodologies, and implementation flows.
Santa Clara, CA30+ days ago
p>• Develop analog and mixed-signal architectures and circuits in CMOS or BiCMOS processes • Analyze technology, architecture, circuit design, and parametric design trade-offs to meet aggressive technical performance specifications • Perform transistor-level design and simulation using industry leading EDA tools • Lead comprehensive design reviews • Supervise Analog Circuit Physical Design Layout and edit layouts • Collaborate with Digital Design Engineers, CAD, Systems Engineering, Test Engineering and Applications teams to ensure DFT, DFM features and achieve rapid silicon bring-up and time to production release • Work closely with the verification team to define the verification matrix • Have the ownership of the top-level schematic and run all the top-level analog simulation • Participate in top-level AMS verification. Proven track record at each stage of the following:
• Circuit architecture development and technical feasibility studies • Writing detailed block-level specifications and review documents • Detailed design and simulation of one or more of the following: • Oscillators • ADCs • DACs • Temperature sensors • Integer and Fractional-N PLLs • Digital PLLs • Low-noise op-amps • Regulators • Bandgap circuits in CMOS or BiCMOS processes • Subthreshold circuits and architecture.
Santa Clara, CA30+ days ago
Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. Experience with architecture, design, and production expertise in the following areas:
Architectural investigations and implementation for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs,ADC etc.
Sunnyvale, California28 days ago
The role requires extensive experience in ASIC design and layout—including top-level ownership of ASIC tape-outs at leading commercial foundries—and deep expertise in either or both of these two categories: high-precision AMS circuits and high-speed wireline/silicon photonics interface circuits. Demonstrated deep design expertise in one or both of the following categories:
High-precision designs: Analog-to-digital and digital-to-analog converters, bandgap references, voltage regulators, amplifiers, and other supporting circuitry.
Alameda, California30+ days ago
p style="min-height:1.5em">Ideal candidate would take ownership of modules/blocks – specification-to-design life cycle – and document/perform: architecture exploration, transistor-level design, pre- and post-layout simulation, and Monte Carlo/SOA/reliability/aging verification. The candidate would be comfortable with ambiguity that comes with working in compact and fast-paced environments, and be willing to involve in ancillary activities, such as post-silicon bring-up/debug and validation/characterization.
Santa Clara, CA30+ days ago
Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
Cupertino, CA30+ days ago
Engage with cross-functional analog, digital, DV, firmware, software, SoC architecture, technology, packaging, silicon validation, production test, manufacturing, and other teams to implement the new circuits and sub-systems and drive them into production. Experience in working with product and production test engineers to develop and validate test plans, optimize production testing, and debug sources of low-DPPM parametric yield loss is highly valued.
San Francisco, California19 days ago
p/>This role provides the opportunity to work across a wide technical spectrum, from low‑noise, low‑level signal measurement to high‑voltage and high‑frequency electronics, including systems that generate and control thousands of volts at GHz‑range frequencies.
The full-time equivalent pay range for this position is $124,976.00 - $219,000.00/yr plus eligibility for bonus, stock and benefits.
San Jose CA, California30+ days ago
Ensure power integrity for sensitive ADC and high-speed SerDes subsystems. Define FPGA-centric system architectures for high-throughput data processing platforms.
Santa Clara, CA30+ days ago
p>As a member of our Mixed Signal Design Validation team, you will be responsible for the bring-up and characterization of high-speed mixed-signal circuits, in addition to performing system validation of electro-optical transceivers. More recently, GPU deep learning ignited modern AI - the next era of computing - with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world.
Cupertino, CA30+ days ago
Define and specify requirements for analog IP provided by external vendors Drive technical discussions with vendors and foundries Supervise IP design, characterization, and debug Review and sign off of IP design/tools/flow/collaterals, test plans, characterization reports Support Apple IP integration teams including front-end design, design verification, physical design, DFT, TE/PE, SIPI Support Apple system teams with product integration, HW/SW bring up, and debugBSEE/MSEE plus a minimum 7 years of experience in analog IC design. As a member of our dynamic group, you will have the rare and great opportunity to work on upcoming products that will delight and encourage millions of Apple's customers every day!
Santa Clara, CA30+ days ago
This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits.
Santa Clara, CA30+ days ago
This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence! The base salary range is $136,000 USD - $218,500 USD for Level 3, and $168,000 USD - $264,500 USD for Level 4. You will also be eligible for equity and benefits.