div>Our compensation reflects the cost of labor across several U.S. geographic markets, and we pay differently based on those defined markets.
- BS in Electrical Engineering or a related field plus minimum 4 years of industry experience in analog and/or mixed-signal circuit design (or MS plus minimum 2 years of industry experience).
Santa Clara, CA30+ days ago
Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. Experience with architecture, design, and production expertise in the following areas:
Architectural investigations and implementation for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs,ADC etc.
Santa Clara, CA30+ days ago
p>• Develop analog and mixed-signal architectures and circuits in CMOS or BiCMOS processes • Analyze technology, architecture, circuit design, and parametric design trade-offs to meet aggressive technical performance specifications • Perform transistor-level design and simulation using industry leading EDA tools • Lead comprehensive design reviews • Supervise Analog Circuit Physical Design Layout and edit layouts • Collaborate with Digital Design Engineers, CAD, Systems Engineering, Test Engineering and Applications teams to ensure DFT, DFM features and achieve rapid silicon bring-up and time to production release • Work closely with the verification team to define the verification matrix • Have the ownership of the top-level schematic and run all the top-level analog simulation • Participate in top-level AMS verification. Proven track record at each stage of the following:
• Circuit architecture development and technical feasibility studies • Writing detailed block-level specifications and review documents • Detailed design and simulation of one or more of the following: • Oscillators • ADCs • DACs • Temperature sensors • Integer and Fractional-N PLLs • Digital PLLs • Low-noise op-amps • Regulators • Bandgap circuits in CMOS or BiCMOS processes • Subthreshold circuits and architecture.
Santa Clara, CA30+ days ago
Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
Cupertino, CA30+ days ago
Engage with cross-functional analog, digital, DV, firmware, software, SoC architecture, technology, packaging, silicon validation, production test, manufacturing, and other teams to implement the new circuits and sub-systems and drive them into production. Experience in working with product and production test engineers to develop and validate test plans, optimize production testing, and debug sources of low-DPPM parametric yield loss is highly valued.
Sunnyvale, California28 days ago
The role requires extensive experience in ASIC design and layout—including top-level ownership of ASIC tape-outs at leading commercial foundries—and deep expertise in either or both of these two categories: high-precision AMS circuits and high-speed wireline/silicon photonics interface circuits. Demonstrated deep design expertise in one or both of the following categories:
High-precision designs: Analog-to-digital and digital-to-analog converters, bandgap references, voltage regulators, amplifiers, and other supporting circuitry.
San Jose CA, California30+ days ago
Ensure power integrity for sensitive ADC and high-speed SerDes subsystems. Define FPGA-centric system architectures for high-throughput data processing platforms.
Santa Clara, CA30+ days ago
p>As a member of our Mixed Signal Design Validation team, you will be responsible for the bring-up and characterization of high-speed mixed-signal circuits, in addition to performing system validation of electro-optical transceivers. More recently, GPU deep learning ignited modern AI - the next era of computing - with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world.
Santa Clara, CA30+ days ago
This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits.
Santa Clara, CA30+ days ago
This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence! The base salary range is $136,000 USD - $218,500 USD for Level 3, and $168,000 USD - $264,500 USD for Level 4. You will also be eligible for equity and benefits.
Sunnyvale, CA30+ days ago
p>The CMOS Mixed-Signal Circuit Design Engineer contributes to the development of advanced mixed signal circuits for low-power and high performance PLLs, PVT sensors and I/O's to be used in numerous products from high performance data center SoCs to low power consumer SoCs. We specialize in developing advanced mixed signal circuits for low power, high-speed, Fin-FET mixed-signal and analog IPs that are used in numerous products from high performance data center SoCs to low power consumer SoCs.
Sunnyvale, CA30+ days ago
p>PREferred SKILLS AND EXPERIENCE: • Master's degree or PhD in electrical engineering, computer engineering with emphasis in electromagnetic theory, transmission line theory, wireline transceivers, or power integrity • 5+ years of electronic product experience designing hardware from concept through production; strong emphasis on full life-cycle development of new hardware products and not small incremental updates to legacy hardware • 5+ years of experience architecting, implementing, and debugging cutting edge DSP based SERDES products (i.e. 56Gbps, 112Gbps, 224Gbps) working across package and PCB • 5+ years of experience specifying, analyzing, debugging, and working with high speed, high bandwidth memory interfaces • 5+ years of experience designing, implementing, and debugging power delivery networks for large processors, FPGAs, SoC, or ASICs with complex power requirements • Thorough understanding of wireline transceiver concepts, architectures, and circuits • Strong understanding of computers and programming languages (Python, C/C++) • Demonstrated ability to work in a highly cross-functional role • Experience with low loss laminates, high volume PCB manufacturing, and high-speed connectors • Experience debugging and resolving EMI/EMC de-sense problems • Passion for working in dynamic cross-functional role to optimize package, PCB, ASIC, mixed signal circuit to deliver best in class products.
BASIC QUALIFICATIONS:
• Bachelor's degree in electrical engineering, computer engineering, or physics • 5+ years of industry experience designing circuits, electronic products, or hardware • 2+ years of experience using one of the 3D EM simulation tools and high-speed digital channel simulators (CST, HFSS, ADS etc.) • 2+ years of research or industry experience with high-speed digital design or power integrity.
Santa Clara, CA30+ days ago
p>What we need to see: • MS and/or PhD in Electrical and Computer Engineering (or equivalent experience) with minimum 2 years of work experience MS and/or PhD in Electrical and Computer Engineering (or equivalent experience) with minimum 2 years of work experience.
• Familiarity with use of VNA, TDR, DSO, ParBERT and use of tools/applications like ADS, Ansys Designer, JMP, Matlab, Cadence Allegro.
San Jose CA, California30+ days ago
Oscilloscopes, function generators, spectrum analyzers, network analyzers. Minimum 5+ years of experience in analog or mixed-signal circuit design (PhD graduates may qualify with less experience).
Mountain View, CA30+ days ago
The Role: The Senior Signal Integrity Engineer at General Motors plays a crucial role in ensuring the performance and reliability of high-speed hardware designs within the ECU Electrical team. Our vision is a world with Zero Crashes, Zero Emissions and Zero Congestion and we embrace the responsibility to lead the change that will make our world better, safer and more equitable for all.
Sunnyvale, CA30+ days ago
The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Lead the development of next-generation memory interfaces and evaluate high-speed interface IP, considering Input/Output Physical Layer (IO PHY), physical design, and SI/PI requirements.
Santa Clara, CA30+ days ago
p>Lead and drive the creation of validation test plan and test scripts for DDR I/O associated with LPDDR, GDDR, and HBM memory interfaces, ensuring all necessary required analog and digital circuits are covered. Work closely with multi-functional teams, including Mixed signal design, PISI team, hardware, firmware, and Memory qualification engineer, to resolve issues and improve the performance for memory interfaces.
Santa Clara, CA30+ days ago
MS/PhD in Electrical Engineering and 10+ years of demonstrated experience in high-speed and low-power design on advanced CMOS technologies in the following areas: Analog Front Ends (TX Driver, TIA, CTLE, VGA), Data Converters, Voltage Regulators, Clock Generation and Distribution, DLLs, custom high-speed digital circuits. Design and develop high-speed and low-power analog mixed-signal circuits in advanced CMOS technologies, with a focus on SerDes (Serializer/Deserializer) die-to-die communication, and high-speed wireline design in general.
The hardware validation team ensures that this equipment operates properly electrically, functions as intended, meets quality requirements, and exhibits the level of reliability expected by customers. As a hardware validation engineer, you will qualify networking hardware like switches, smart-network interface cards, custom cables, and other specialized hardware for Google"s data centers.
Mountain View, CA30+ days ago
By leveraging cutting-edge automation and academic research collaborations, we solve critical hardware challenges to ensure the performance and robustness of Google"s flagship devices. Collaborate cross-functionally with Architecture, Silicon, and Product Design teams to resolve complex electrical design trade-offs.
p>Business group: The Central Engineering Group (CEG) is Intel''s data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). Applies various strategies, tools, and methods for mixed signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Palo Alto, CA30+ days ago
Our application, software, and industry teams work directly with leading Fortune 500 companies-including Lockheed Martin, Mercedes-Benz, Boehringer Ingelheim, and Mitsubishi Chemical-to prepare quantum solutions for real-world impact. Actual compensation may vary outside of these ranges and is dependent on various factors including but not limited to a candidate's qualifications including relevant education and training, competencies, experience, geographic location, and business needs.
p>Google"s Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. Design, develop, and debug multi-site ATE test programs (Advantest V93000 or Teradyne UltraFLEX) focusing on high-efficiency parallel testing for digital and AMS blocks.
Sunnyvale, CA30+ days ago
From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving channel behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Bachelor''s degree in Electrical Engineering and 8+ years of relevant signal and power integrity experience, or Master''s degree in Electrical Engineering and 6+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 3+ years of relevant signal and power integrity experience.
p>Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Strong knowledge of analog/mixed‑signal circuits such as op‑amps, bandgap, regulators, comparators, equalization circuits, PLL/DLL, and phase interpolators.
p>InvenSense's motion tracking, audio and location platforms, and services can be found in many of the world's largest and most iconic brands including smartphones, tablets, wearables, drones, gaming devices, internet of things, automotive products, and remote controls for smart TVs. Strong skills in designing various analog/mixed-signal blocks including:
• MEMS sense amplifiers (precision switched-capacitor OPAMP) • Analog-to-Digital Converter (ADC) • Bandgap references • Charge pumps • Oscillator circuits.
Santa Clara, CA22 days ago
Job Title: Analog Design Engineer Job Duties:Conduct design and development of image sensor technologies, work on transistor level design of analog and mixed-signal circuits for CMOS Image Sensor such as asic_pixel array, column-amplifier, switch capacitor, comparator, ramp generator, ASRAM and XDEC by using Cadence Virtuoso. Design the internal Discrete-time Circuits, Peripheral circuits and Timing control for a CMOS image sensor, including bias circuits, driver/level shifter, switched capacitor, logic gates and slew rate control.
p>Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Strong knowledge of analog/mixed‑signal circuits such as op‑amps, bandgap, regulators, comparators, equalization circuits, PLL/DLL, and phase interpolators.