Soc Verification Engineer Intel Corp.Soc Verification EngineerSanta Clara, CA$141,910–$200,340 / yearBachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 4+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning. Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 3+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning.
Sr. ASIC Verification Engineer Recogni IncSr. ASIC Verification EngineerSunnyvale, CAResponsibilities: Your responsibilities will be wide-ranging and and run the gamut of working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular SystemVerilog and UVM, handling bug tracking and coverage convergence and developing scripts and methodologies for the front-end ASIC flow. This ASIC's design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to deliver the high-performance multi-chip silicon solutions that are at the heart of Tensordyne's vertically integrated, generative AI inference acceleration systems for data centers.
Sr. Staff ASIC Verification Engineer Recogni IncSr. Staff ASIC Verification EngineerSunnyvale, CAResponsibilities: Your responsibilities will be wide-ranging and and run the gamut of working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular SystemVerilog and UVM, handling bug tracking and coverage convergence and developing scripts and methodologies for the front-end ASIC flow. This ASIC's design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to deliver the high-performance multi-chip silicon solutions that are at the heart of Tensordyne's vertically integrated, generative AI inference acceleration systems for data centers.
ASIC Verification Engineer Axiado CorpASIC Verification EngineerSan Jose, CAAxiado has also won numerous industry awards for our ground-breaking products and technological innovations, including being named one of Fast Companys 2025 Top 10 Most Innovative Companies in Security, winning the 2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliances 2025 Start-Up to Watch award. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management.
SR Design Verification Engineer Advanced Micro Devices, IncSR Design Verification EngineerSanta Clara, CaliforniaOur distributed services platform expands AMD’s data center product portfolio with a high‑performance DPU and software stack deployed at scale across major cloud and enterprise environments, including Goldman Sachs, IBM Cloud, Microsoft Azure, and Oracle. The ideal candidate brings hands‑on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading verification efforts across IP, subsystem, and SoC levels.
Sr. Design Verification Engineer Advanced Micro Devices, IncSr. Design Verification EngineerSanta Clara, CaliforniaYou will develop and enhance CPU-level testbenches used by core verification and debug teams to validate complex subsystems, working closely with globally distributed engineering teams. This role focuses on enabling high-quality CPU verification through robust infrastructure and offers exposure to advanced methodologies, including AI-driven development and debug, to improve efficiency and accelerate product delivery.
IP Design Verification Engineer Intel Corp.IP Design Verification EngineerSanta Clara, CA$141,910–$200,340 / yearThe candidate must have a Bachelor's degree in Electrical/Computer Engineering or Computer Science and 5+ years of experience- OR- Master's degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience- OR- PhD in Electrical/Computer Engineering or Computer Science and 2+ years of experience. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.
Sr. Design Verification Engineer DustPhotonics LtdSr. Design Verification EngineerSan Jose, CA$130,000–$160,000 / yearOur product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. You'll develop and execute verification plans, build scalable reusable testbenches, write SV‑UVM sequences, debug issues, and collaborate closely with RTL designers and firmware/application engineering teams.
Senior Design Verification Engineer Advanced Micro Devices IncSenior Design Verification EngineerSanta Clara, CAYou will develop and enhance CPU-level testbenches used by core verification and debug teams to validate complex subsystems, working closely with globally distributed engineering teams. This role focuses on enabling high-quality CPU verification through robust infrastructure and offers exposure to advanced methodologies, including AI-driven development and debug, to improve efficiency and accelerate product delivery.
Principal Design Verification Engineer Microsoft CorpPrincipal Design Verification EngineerMountain View, CA$142,800–$274,800 / yearThe AI Silicon Engineering (AISiE) SoC Design Verification team is seeking passionate, driven, and intellectually curious silicon verification engineers who can work with cross-discipline teams (including systems, firmware, architecture, design, validation, and product engineering) to develop environment and test cases to verify Microsoft's latest AI accelerators. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.
Senior Verification Engineer Microsoft CorpSenior Verification EngineerMountain View, CA$119,800–$234,700 / yearRequired Qualifications: Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Masters Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
NewSr Staff - Staff Design Verification Engineer Sa Technologies, Inc.Sr Staff - Staff Design Verification EngineerSunnyvale, CAAs a CMMI Level 5 and Great Place to Work Certified global IT consulting and services company-and recognized as one of the Best Places for Women-we are committed to building an inclusive, supportive, and high-performance workplace Job Description Key Responsibilities · Work with architects, designers, post silicon and software engineers to ensure a high-quality design that works first silicon. · Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, and gate level simulations.
Sr. Design Verification Engineer Credo Semiconductor, Inc.Sr. Design Verification EngineerSan Jose, CA$130,000–$160,000 / yearOur product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. You'll develop and execute verification plans, build scalable reusable testbenches, write SV-UVM sequences, debug issues, and collaborate closely with RTL designers and firmware/application engineering teams.
Sr Staff – Staff Design Verification Engineer SA TechnologiesSr Staff – Staff Design Verification EngineerSunnyvale, CAAs a CMMI Level 5 and Great Place to Work® Certified global IT consulting and services company—and recognized as one of the Best Places for Women—we are committed to building an inclusive, supportive, and high-performance workplace. · Work with architects, designers, post silicon and software engineers to ensure a high-quality design that works first silicon.
Verification Engineer - Aeromechanical (Design & Test) PivotalVerification Engineer - Aeromechanical (Design & Test)Palo Alto, CaliforniaDemonstrates a proactive safety mindset by embedding safety into daily operations, identifying and mitigating risks through assessments and training, encouraging open dialogue on safety concerns, and continuously improving protocols to ensure a safe work environment. Actively seeks and values diverse stakeholder perspectives, builds cross-functional relationships, and fosters trust through empathetic, fact-based communication—committing to shared decisions for the greater good.
Staff ASIC Design Verification Engineer Google LLCStaff ASIC Design Verification EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing with key teams working on the development of our TPUs Vertex AI for Google Cloud Google Global Networking Data Center operations systems research and much more. Were the driving force behind Googles groundbreaking innovations empowering the development of our cutting-edge AI models delivering unparalleled computing power to global services and providing the essential platforms that enable developers to build the future.
Design Verification Engineer MythicDesign Verification EngineerPalo Alto, CA$120,000–$225,000 / yearBecause today's AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently. We've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets.
Senior Design Verification Engineer MythicSenior Design Verification EngineerPalo Alto, CA$120,000–$225,000 / yearDesign Verification at Mythic: At Mythic, our Design Verification (DV) team is central to ensuring the correctness and reliability of our novel digital dataflow architecture, which includes a sophisticated scheduling subsystem, high-performance interconnect fabric, and advanced DMA engines that work together with our Analog Compute Engines to accelerate AI workloads. Because today's AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently.
Senior Design Verification Engineer, Silicon Google LLCSenior Design Verification Engineer, SiliconMountain View, CAExecute gate-level simulations (GLS) and Unified Power Format (UPF)-based power simulations, performing debugging to deliver high-performance and low-power hardware. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement.
Sr. Reliability/Verification Engineer Ouster IncSr. Reliability/Verification EngineerSan Francisco, CA$140,000–$200,000 / yearThe Industrial Autonomy Team is seeking a senior reliability and verification engineer to design the test frameworks and validation strategies proving our products for autonomy and physical AI customers are safe and rugged. Within our small hardware team, you will be the gatekeeper for reliability, ensuring our compute, electromechanical, and safety-critical platforms survive harsh environments for customer deployment at scale.
Senior Silicon Design Verification Engineer, YouTube Video Accelerators Google LLCSenior Silicon Design Verification Engineer, YouTube Video AcceleratorsMountain View, CAAs a part of the Design Verification (DV) role in the Argos IP team, you will ensure the functional correctness of custom video codec ASICs for YouTube by managing a specialized High-Level Synthesis (HLS) workflow that requires verification at both the C/C++ and RTL levels. You will be responsible for bridging the gap between algorithmic intent and hardware implementation, employing a hybrid strategy that includes C++ software testing, C/RTL co-simulation, and traditional SystemVerilog/ Universal Verification Methodology (UVM) testbenches to guarantee equivalence and compliance.
Sr. Software System Verification Engineer ShifamedSr. Software System Verification EngineerLos Gatos, CaliforniaSupira Medical, a clinical-stage Shifamed Portfolio Company, is developing a low-profile, high continuous flow percutaneous ventricular assist device (pVAD) to provide temporary mechanical circulatory support in high risk percutaneous coronary interventional (HRPCI) procedures as well as patients suffering from cardiogenic shock. Founded in 2009 by serial entrepreneur Amr Salahieh, Shifamed LLC is a privately held medical device innovation hub focused on the development of novel medical products to address clinical needs in the rapidly evolving fields of cardiology and ophthalmology.
CPU SoC Verification Engineer Google LLCCPU SoC Verification EngineerMountain View, CAGoogle is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement.
Senior ASIC Verification Engineer Hewlett Packard EnterpriseSenior ASIC Verification EngineerSunnyvale, CaliforniaPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.
NewSenior ASIC Verification Engineer Hewlett Packard Enterprise CoSenior ASIC Verification EngineerSunnyvale, CA$153,500–$310,500 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
ASIC Verification Engineer Hewlett Packard Enterprise CoASIC Verification EngineerSunnyvale, CA$120,000–$243,000 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
NewSenior Asic Verification Engineer Hewlett Packard EnterpriseSenior Asic Verification EngineerSunnyvale, CA$153,500–$310,500 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
CPU Verification Engineer (Multiple Locations) Qualcomm IncCPU Verification Engineer (Multiple Locations)Santa Clara, CA$167,100–$250,700 / yearDeep knowledge of Micro-Processor Verification functions and Architectures, in domains such as: Cache Coherence, Memory ordering and Consistency, Prefetching, Branch Prediction, Renaming, Speculative execution, and Address Translation/Memory Management. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
ASIC Verification Engineer Hewlett Packard EnterpriseASIC Verification EngineerSunnyvale, CaliforniaPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.
Engineering - FPGA Design/Verification Engineer The Structures Company, LLCEngineering - FPGA Design/Verification EngineerSunnyvale, CACross discipline collaboration with Systems Architects, RF/Analog & Digital Circuit designers and ASIC/FPGA engineers to create leading edge products for future business growth, contributing to complex systems employing high speed networking concepts. This engineer with have experience in developing, testing, and integrating digital signal processing (DSP), high speed digital design, high speed communication and system-on-chip (SOC) implemented on FPGA platforms.
Digital Verification Engineer Neuralink CorpDigital Verification EngineerSouth San Francisco, CA$131,000–$243,000 / yearThe team delivers architecture and logic implementation of digital modules with a strong focus in high-throughput low-power digital signal processing (DSP). These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.
Design Verification Engineer Pyramid Consulting, IncDesign Verification EngineerSan Franscisco, CA$160,000–$170,000 / yearBS in Electrical Engineering / Computer Engineering and 8+ years of related experience or an MS in Electrical Engineering / Computer Engineering and 6+ years of related experience. By applying to our jobs you agree to receive calls, AI-generated calls, text messages, or emails from Pyramid Consulting, Inc. and its affiliates, and contracted partners.
Sr. Full Chip Physical Verification Engineer Silicon Engineering Space Exploration Technologies CorpSr. Full Chip Physical Verification Engineer Silicon EngineeringSunnyvale, CA$175,000–$280,000 / yearPREFERRED SKILLS AND EXPERIENCE: Experience and deep understanding of SOC top level physical design flows (floor-planning, I/O, bump & RDL planning, hard IP integration, partitioning, power/ground grid generation, pin assignment, DFT, partition hardening, special clock handling, feedthrough flows, special interface/interconnect planning and implementation). We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Design Verification Engineer Baidu USADesign Verification EngineerSunnyvale, CaliforniaYou will help on UVM Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development. Work closely with the design and systems engineering teams to review specifications and architecture, extract features, define verification plan & coverage model.
Senior ASIC Verification Engineer (AI Hardware) 4 Staffing CorpSenior ASIC Verification Engineer (AI Hardware)San Jose, CaliforniaOur client an AI / Compute company of the verge of being the next Nvidia is looking for an experienced ASIC Verification Engineer to help ensure the quality, reliability, and performance of their next-generation AI-focused silicon. In this role, you'll partner closely with design, architecture, and software teams to validate complex hardware systems and contribute to cutting-edge compute solutions.
CPU Processor Performance Verification Engineer Apple IncCPU Processor Performance Verification EngineerSanta Clara, CAWork closely with OS and compiler teams on system and application performance tuningMinimum BS and 3+ years of relevant industry experience Performance modeling, processor verification, or RTL design experience Experience in digital logic design, CPU architecture, and microarchitecture Experience in developing performance test plans and writing/debugging assembly tests for performance correlation and verification Programming skills in assembly, C/C++, Verilog, System Verilog, or scriptingExperience in benchmark and workload analysis and CPU performance profiling Knowledge of compiler techniques and OS for performance optimization Knowledge in developing instruction profiling tools on silicon Experience in performance modeling for advanced CPU designs Experience in silicon validation Ability to work across teams to optimize silicon performance Should be a great teammate with excellent communication and presentation skills and able to work independently on the owned unit. As a CPU Processor Performance Verification Engineer owning the verification of a certain area of performance features in a chip design, you will have responsibilities as follows: Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon).
Principal Design Verification Engineer (Silicon Engineering) Space Exploration TechnologiesPrincipal Design Verification Engineer (Silicon Engineering)Palo Alto, CA$210,000–$355,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Sr. ASIC Design Verification Engineer (Silicon Engineering) SpaceXSr. ASIC Design Verification Engineer (Silicon Engineering)Palo Alto, CA$175,000–$280,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
Principal Design Verification Engineer (Silicon Engineering) SpaceXPrincipal Design Verification Engineer (Silicon Engineering)Sunnyvale, CA$210,000–$310,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
Sr. Asic Design Verification Engineer (Silicon Engineering) Space Exploration TechnologiesSr. Asic Design Verification Engineer (Silicon Engineering)Palo Alto, CA$175,000–$280,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Senior Formal Verification Engineer AuradineSenior Formal Verification EngineerSanta Clara, CA$200,000–$500,000 / yearOwn and drive formal verification for complex SoC blocks-CPUs, control processors, floating-point units, vector/SIMD engines, and datapath-heavy designs. You will apply formal methods to the hardest correctness problems in the design, working with architects, RTL, and verification teams to prove correctness exhaustively and reach coverage that simulation cannot.
Design verification Engineer ApolisDesign verification EngineerSan Jose, CA$65–$70 / hourA bachelor’s degree in electrical or computer engineering, accompanied by a minimum of 8 years of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline. Key Skill: SV/UVM, AXI expertise, NOC/Crossbar, Performance.
Design Verification Engineer-System Verilog/UVM Advanced Micro Devices, IncDesign Verification Engineer-System Verilog/UVMSan Jose, CaliforniaWe push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Working across a multi-site, global engineering organization, you will drive high-quality verification execution from feature definition through silicon readiness. .
ASIC Design Verification Engineer, TPU GoogleASIC Design Verification Engineer, TPUSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
ASIC Design Verification Engineer, Technical Leader Cisco Systems IncASIC Design Verification Engineer, Technical LeaderSan Jose, CA$183,800–$263,600 / yearWho We Are: The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. For quota-based incentive pay, Cisco typically pays as follows: 75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and.
Sr. FPGA Verification Engineer Reliable Robotics CorporationSr. FPGA Verification EngineerMountain View, CaliforniaFPGA engineers at Reliable Robotics have a unique opportunity to work at the heart of a vertically integrated technology stack that goes all the way up to aircraft level, with a direct impact on the aircraft's capabilities and requirements. FPGA Verification Engineer, you will own the FPGA integration and test environment for multiple airborne products including their test benches & simulation, continuous integration, timing analysis, elemental analysis, and build.
Silicon Design Verification Engineer-FPGA/System Verilog Advanced Micro Devices, IncSilicon Design Verification Engineer-FPGA/System VerilogSan Jose, CaliforniaYou will plan, develop, and execute comprehensive verification strategies across complex digital subsystems, working closely with cross-functional engineering teams to deliver robust, bug-free designs. You bring strong analytical and debugging skills, communicate effectively across globally distributed teams, and are motivated to learn new technologies while taking ownership of difficult problems.
Senior Design Verification Engineer Altera SemiconductorSenior Design Verification EngineerSan Jose, California$142.60–$206.50 / hourAltera is responsible for High-Speed Protocol IP development, which includes participating in high-level product specifications, logic/RTL design and implementation, RTL verification, IP FPGA validation and debugging. As Lead DV Engineer focusing on IP Verification & Validation, you will be responsible for carrying out design validation for Altera next generation IP's across the Altera FPGA IP product portfolios.
NewSr. FPGA Design & Verification Engineer Dolby Laboratories IncSr. FPGA Design & Verification EngineerSan Francisco, CA$137,100–$188,300 / yearDolby's consumer entertainment and cinema businesses are bringing Dolby's breakthrough technologies, powering the world's top movies, TV shows, music, games, and live sports to more places around the world across a wider range of consumer experiences and devices. Using disciplined engineering practices such as coverage-driven verification, design automation, and continuous process improvement, youll help deliver the quality and reliability that define Dolbys industry-leading cinema products.
Verification Engineer III eTeam Inc.Verification Engineer IIISunnyvale, CAUsing verification skills to define verification requirements, create test cases, design and implement the testing infrastructure, execute the testing, and report the results for the new product designs. Working closely with researchers, architects, and designers in architecting methods of electrical verification for multiple state of the art systems.