PERMANENT

FEED

UNKNOWN

Design, build, validate, and automate RF test benches for full characterization of custom RF designs, often involving vector network analyzers (VNA), vector signal generators (VSG), vector signal analyzers (VSA), spectrum analyzers, load pulls, RF power meters, high-speed oscilloscopes, and other common lab equipment. As an RF software engineer in the Starlink program, you will work with a team of RF engineers, DSP engineers, software engineers, hardware engineers, and end users to design and build RF capabilities for proliferated communications and remote sensing in low earth orbit.

SpaceX

RF Software Engineer (Starlink)

greenhouse_via_bold

Space Exploration Technologies

ea_via_bold

ADAPTED_NOW

The Skyworks RMI-Timing Systems Engineering Team is an elite group of system design engineers focused on developing products and solutions for attractive market opportunities in the form of reference designs, derivative ICs with embedded firmware, and packages. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management, and the freedom to make meaningful contributions in a setting that encourages creative thinking.

YEAR

Skyworks Solutions, Inc

Staff Systems Engineer (Austin, TX, US)

Advanced knowledge and understanding of High Voltage substation components: Transformers, Circuit Breakers, Disconnect Switches, Circuit Switchers, Capacitor Banks, Station Service Transformers, Reactors, Rigid Bus, Gas Insulated Substation (GIS), Switchgear buildings, Control house, underground cable potheads, etc is strongly preferred. You will play a crucial role in directly interfacing with utility/developer clients on development of Substation design deliverables for utility upgrades including greenfield/brownfield & AIS/GIS substations, offshore wind facilities, and developer interconnection facilities.

Jacobs Solutions Inc

Substation Project Engineer

OTHER

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues   .

Advanced Micro Devices, Inc

Emulation Verification Engineer

[AW]-iCims

Amphenol Corporation is one of the world’s largest designers and manufacturers of electrical, electronic and fiber optic connectors and interconnect systems, antennas, sensors and sensor-based products and coaxial and high-speed specialty cable. FCI Basics, an Amphenol business approaching $500 million in annual revenue , is seeking a driven, hunter-style Application Development Engineer to develop new opportunities and grow strategic customer relationships across North America.

Amphenol TCS

Application Development Engineer

AcquireTM

From the smartphones in our pockets that access the world's collective knowledge, to the cloud-based services where all that information lives, to high-speed wireless communication and computing power needed to drive artificial intelligence, augmented and virtual reality, gaming and so much more, our technology is all around us. Veecos laser annealing portfolio is expanding into new applications across advanced node manufacturing, creating a need for an Applications Engineer who can translate customer challenges into production-ready process solutions.

Veeco Instruments Inc

Product Applications Engineer

Whether you've got deep experience in commercial real estate, skilled trades or technology, or you're looking to apply your relevant experience to a new industry, join our team as we help shape a brighter way forward. The Operating Engineer will be responsible for operating, maintaining, and repairing building mechanical systems to ensure optimal performance, energy efficiency, and occupant comfort.

Jones Lang LaSalle Inc

Operating Engineer

The individual will have a role in implementing the overall system architecture, designing transistor-level analog circuit blocks, simulating sub-system performance, creating and using behavioral models of blocks and the entire IC, doing and/or supervising physical layout and verifying circuit and chip-level operation and performance. Seeking an experienced Analog/Power IC design engineer for developing complex analog mixed signal/integrated power management ICs for Industrial Control, Industrial Power, Isolation, and other Infrastructure applications.

Sr. Electrical Engineer (Austin, TX, US)

THE ROLE: The Data Center Facility Design Engineer leads the end‑to‑end design, construction consultation, and operational readiness of customer data center environments, ensuring resilient, efficient, and scalable infrastructure across power, cooling, networking, and facility systems. They are comfortable owning problems end‑to‑end-from design reviews to root‑cause analysis-and excel at translating engineering requirements into practical, scalable facility solutions that support high‑density compute and AI cluster deployments.

Advanced Micro Devices Inc

Data Center Facility Design Engineer

Experience delivering telemetry and remote monitoring at scale, and integrating RTUs, substations, and field devices into a coherent operational picture. We are working directly with one of the largest compute providers to make our vision come true and plan to deploy 5GWs by 2028.

Substation Automation Engineer

Experience with high-speed/RF lab equipment including oscilloscopes, BER testers, vector network analyzers, phase noise analyzers. The Analog Validation Engineer / Architect is responsible for comprehensive validation of key product indicators (KPI's) as defined in the system compliance matrix for all analog circuitry in any given platform.

NXP Semiconductors NV

Sr. Analog Validation Engineer

Principal Analog Validation Engineer

Collaborate with Cross-Functional Teams: Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create timing constraints, and drive timing and power convergence as well as implement ECOs. What you'll be doing: Drive Timing Analysis and Closure: Lead the timing analysis and closure processes for NVIDIA's GPUs, CPUs, LPUs, and SoCs at block level, cluster level, and full chip level.

Visualize your future . . . We Do 
NVIDIA is the world leader in graphics processing technologies, creating innovative, industry-changing products for computing, consumer electronics, and mobile devices. NVIDIA products are transforming visually-rich applications such as video games, film production, broadcasting, industrial design, space exploration, and medical imaging. We invest in our people and our technologies, support and fund industry research around the world, and consistently deliver high-quality products. NVIDIA's culture promotes and inspires a team of world-class employees to be at the top of their game. We've created an environment where talents are recognized and collaboration is valued. Our employees are shaping the world of tomorrow. . . today. We invite you to explore the opportunities available at NVIDIA to see what your future may hold.

NVIDIA Corp

Senior ASIC Timing Engineer

You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits .

NVIDIA

Senior ASIC Physical Design Engineer, Netlisting

The Maintenance Engineer is responsible for the reliable, safe, and cost‑effective operation of all mechanical, electrical, and instrumentation systems within an industrial chemical wastewater treatment plant and a parallel Ultra‑Pure Water (UPW) production plant. This role leads a multi‑disciplinary maintenance team, drives preventive‑maintenance programs, manages capital‑project upgrades, and ensures compliance with environmental, safety, and quality regulations.

Samsung Electronics America Inc

WTR Maintenance Engineer

Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.

Power Engineer Jobs in Bastrop, TX

RF Software Engineer (Starlink) SpaceX

RF Software Engineer (Starlink) Space Exploration Technologies

Staff Systems Engineer (Austin, TX, US) Skyworks Solutions, Inc

Substation Project Engineer Jacobs Solutions Inc

Emulation Verification Engineer Advanced Micro Devices, Inc

Application Development Engineer Amphenol TCS

Product Applications Engineer Veeco Instruments Inc

Operating Engineer Jones Lang LaSalle Inc

Sr. Electrical Engineer (Austin, TX, US) Skyworks Solutions, Inc

Data Center Facility Design Engineer Advanced Micro Devices Inc

Substation Automation Engineer TAR

Sr. Analog Validation Engineer NXP Semiconductors NV

Principal Analog Validation Engineer NXP Semiconductors NV

Senior ASIC Timing Engineer NVIDIA Corp

Senior ASIC Physical Design Engineer, Netlisting NVIDIA

WTR Maintenance Engineer Samsung Electronics America Inc

Senior ASIC Design Engineer – Clocks IP NVIDIA

ASIC Design Engineer – Clocks IP NVIDIA

Asic Design Engineer - Clocks IP Nvidia

Senior Asic Design Engineer - Clocks IP Nvidia

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