FEA Packaging Engineer CspeedFEA Packaging EngineerPalo Alto, CaliforniaOur executive team has a demonstrated track record of building and scaling category-defining semiconductor and infrastructure businesses at companies like Broadcom, Lumentum, Tesla, Apple, Samsung, Intel, and VMware. Expert proficiency in one commercial FEA or CFD tool and working proficiency in a second covering the other domain — for example Ansys Mechanical or Abaqus alongside Icepak, Fluent, Flotherm, or Celsius.
Memory Packaging Engineer MediaTek IncMemory Packaging EngineerSan Jose, CACollaborate closely with IP, ASIC design, package design, Signal Integrity (SI), Power Integrity (PI), Thermal and modeling technologies, Product Engineering, and Test Engineering teams to enable innovative solutions. Roles and Responsibilities: Supports MediaTek's Memory packaging technology development including but not limited to HBM package, cHBM, LPDDR package for mobile applications, In Package Memory (IPM) for Edge AI, etc.
Advanced Packaging Engineer — Fiber Array Integration CspeedAdvanced Packaging Engineer — Fiber Array IntegrationPalo Alto, CaliforniaA permanently bonded fiber array constrains the downstream flow in three respects: the engine cannot be optically qualified before fiber attach, a single failed channel scraps an assembly containing multiple high-value die, and manual fiber handling limits automation. This position owns the detachable optical interface for CspeedIO optical engines: the on-package element, the coupling optics, the alignment features, and the high-volume assembly process that joins fiber to engine without per-unit active alignment.
Advanced Packaging Integration Engineer Applied MaterialsAdvanced Packaging Integration EngineerSanta Clara, CA$161,000–$221,000 / yearJoin the Photonics Platform Business Group at Applied Materials located in Santa Clara headquarters, work with a high caliber cross-functional research team to develop advanced packaging solutions for next-generation smart glasses and high‑performance optical interconnects. In‑depth knowledge and hands‑on experience in advanced packaging technologies, including wafer‑to‑wafer or die‑to‑wafer hybrid bonding, semiconductor processing, 2.5D/3D integration, TSV, RDL, underfill, bumping, molding, and OSAT processes.
Signal Integrity & Interconnect Engineer - High‑Speed Channels & mmWave Packaging POINT2 TECHNOLOGY INCSignal Integrity & Interconnect Engineer - High‑Speed Channels & mmWave PackagingSan Jose, CADesign and optimize the high‑speed interconnect "highways" that enable Point2's next‑generation ultra‑high‑speed data‑center links. Work across die, package, PCB, and complex mechanical connectors to ensure flawless signal transmission at mmWave and sub‑THz frequencies.
Principal/ Staff Engineer, Advanced Packaging Process Integration Applied Materials IncPrincipal/ Staff Engineer, Advanced Packaging Process IntegrationSanta Clara, CAThe SMTS will operate at the intersection of technology innovation, customer roadmaps, and ecosystem collaboration, translating emerging concepts into scalable, differentiated capabilities aligned with Applied Materials' long-term strategy. You will experiment, learn, and collaborate with some of the brightest minds in the semiconductor and display industries, partnering with our globally recognized R&D teams on state-of-the-art research and development projects.
Global Product Support (GPS) Engineer - Advanced Packaging Applied Materials IncGlobal Product Support (GPS) Engineer - Advanced PackagingSanta Clara, CA$124,000–$171,000 / yearIf you would like to contact us regarding accessibility of our website or need assistance completing the application process, please contact us via e-mail at Accommodations_Program@amat.com, or by calling our HR Direct Help Line at 877-612-7547, option 1, and following the prompts to speak to an HR Advisor. The successful candidate will serve as the primary equipment support engineer responsible for bringing the system from installation through process readiness while coordinating closely with Facilities, BESI, Applied Materials product engineering teams, and CTO process development teams.
Global Product Support (Gps) Engineer - Advanced Packaging Applied MaterialsGlobal Product Support (Gps) Engineer - Advanced PackagingSanta Clara, CA$124,000–$171,000 / yearIf you would like to contact us regarding accessibility of our website or need assistance completing the application process, please contact us via e-mail at Accommodations_Program@amat.com, or by calling our HR Direct Help Line at 877-612-7547, option 1, and following the prompts to speak to an HR Advisor. The successful candidate will serve as the primary equipment support engineer responsible for bringing the system from installation through process readiness while coordinating closely with Facilities, BESI, Applied Materials product engineering teams, and CTO process development teams.
Packaging Mechanical Engineer DensityAIPackaging Mechanical EngineerMountain View, CA$200,000–$275,000 / yearYou'll model warpage and stress through reflow and assembly, design the lid, stiffener, underfill and TIM stack that controls them, set the mechanical rules our OSATs build to, and own the socket and load mechanics where the package meets the cooling solution. Exceptional abilities in thermo-mechanical analysis of semiconductor packages: warpage prediction and control, die and solder-joint stress, delamination and interfacial fracture risk, and material and structural tradeoffs.
Senior Power Integrity Engineer - LPU Packaging NVIDIA CorpSenior Power Integrity Engineer - LPU PackagingSanta Clara, CA$196,000–$310,500 / yearWe have some of the most forward-thinking and hardworking people in the world working with us and our product lines are growing fast in some of the hottest state-of-the-art fields such as Artificial Intelligence, Deep Learning, Autonomous Vehicles, and Robotics. A deep understanding of board-level PDN design, including stack-up definition, plane partitioning, and VRM placement on high-layer-count accelerator boards.
Senior Signal Integrity Engineer - LPU Packaging NVIDIA CorpSenior Signal Integrity Engineer - LPU PackagingSanta Clara, CADevelop and execute simulation flows for advanced packaging technologies, including 2.5D, 3D, and multi-die integration, with strong focus on channel loss, discontinuities, return path behavior, and crosstalk. We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our world-class engineering teams are growing fast.
Senior, Packaging Design Engineer Intuitive Surgical IncSenior, Packaging Design EngineerSunnyvale, CAThis individual will use sound engineering judgement and independently drive new product development (NPD) and sustaining engineering efforts through cross functional collaboration, ensuring designs meet stringent clinical, functional, global regulatory (FDA, ISO 11607, EU), and quality requirements. The Medical Device Packaging Design Engineer is a critical engineering role responsible for the design, development, verification, and launch of next-generation mechanical packaging systems for sterile and non-sterile medical devices such as surgical instruments, disposables, and electromechanical capital equipment.
Process Engineer, Advanced Packaging Applied Materials IncProcess Engineer, Advanced PackagingSanta Clara, CA$124,000–$171,000 / yearIf you would like to contact us regarding accessibility of our website or need assistance completing the application process, please contact us via e-mail at Accommodations_Program@amat.com, or by calling our HR Direct Help Line at 877-612-7547, option 1, and following the prompts to speak to an HR Advisor. The salary offered to a selected candidate will be based on multiple factors including location, hire grade, job-related knowledge, skills, experience, and with consideration of internal equity of our current team members.
Process Engineer - Advanced Packaging Applied Materials IncProcess Engineer - Advanced PackagingSanta Clara, CA$147,000–$202,500 / yearRole Responsibilities: Design, collect data, analyze, and compile results for complex process engineering experiments across multiple process modules; apply findings to establish process baseline, monitor performance and stability. If you would like to contact us regarding accessibility of our website or need assistance completing the application process, please contact us via e-mail at Accommodations_Program@amat.com, or by calling our HR Direct Help Line at 877-612-7547, option 1, and following the prompts to speak to an HR Advisor.
Senior Engineer, Semi Packaging Engineering Analog Devices IncSenior Engineer, Semi Packaging EngineeringSan Jose, CA$109,940–$151,168 / yearADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. This role will work closely with Business Units, global operations, and external partners to deliver robust, scalable NPI packaging solutions while enabling supply chain resilience and continuous improvement in our development systems.
Sr. Industrial Designer (Packaging) SanDisk CorpSr. Industrial Designer (Packaging)Milpitas, CAAn employee's pay position within the salary range may be based on several factors including but not limited to (1) relevant education; qualifications; certifications; and experience; (2) skills, ability, knowledge of the job; (3) performance, contribution and results; (4) geographic location; (5) shift; (6) internal and external equity; and (7) business and organizational needs. Sandisk is looking for a Senior Packaging Industrial Designer to join global industrial design team to design 3D structural packaging solutions for world‑class consumer storage products.
NewPackaging Compliance Analyst Ursus, Inc.Packaging Compliance AnalystFoster City, CA$47–$57.93 / hourAssist in documenting the success or failure of trial packaging, capturing its condition upon reception at the warehouse, and its feasibility for use at the production line with Packaging Engineers, MFEs, MFG, Logistics, suppliers, SSMs, and SQEs. Become fully acquainted with all information systems regarding inventory management and logistics to support reporting, including but not limited to: PFEP, Shipping Label Tracker, Packaging Compliance Tracker, and Logistics KPIs.
Technologist, Packaging Engineering SanDisk CorpTechnologist, Packaging EngineeringMilpitas, CAProvide technical leadership in evaluating and validating design options through characterization builds and comprehensive DFX (Design for excellence) analyses, including DFM (Design for Manufacturability), DFA (Design for Assembly), DFRW (Design for Rework), influencing product architecture and manufacturing strategy at the system level. ESSENTIAL DUTIES AND RESPONSIBILITIES: Serve as the senior Package Engineering representative on cross‑functional leadership teams, setting technical direction and ensuring packages are fully characterized, qualified, and released to production on schedule while meeting stringent mechanical, electrical, performance, reliability, and quality requirements.
Director of Advanced IC Packaging Development Renesas Electronics CorpDirector of Advanced IC Packaging DevelopmentSan Jose, CAWith a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. This role is pivotal in enabling the AI and Datacenter revolution by developing cutting-edge Smart Power Stages, Vertical Power Stages, Power Modules and Wide Bandgap (SiC/GaN) solutions.
Advanced Optical Packaging Design Tech Lead MediaTek IncAdvanced Optical Packaging Design Tech LeadSan Jose, CAThe ideal candidate brings deep expertise in substrate and packaging technologies, hybrid bonding, thermo-mechanical behavior, and high-speed interconnect design, and works effectively across PIC, IC, systems, reliability, manufacturing, and supplier teams. This is a highly visible technical leadership role with responsibility for package architecture, substrate design, hybrid bonding integration, warpage risk management, signal integrity, and production enablement.
Build and OS Packaging Technical Lead, Production Engineering Everpure, IncBuild and OS Packaging Technical Lead, Production EngineeringSanta Clara, CAIn this role, you will drive technical direction, raise engineering execution, and work closely with product, infrastructure, and release teams to improve build performance, reliability, and developer productivity. We have been named Fortune''s Best Workplaces in Technology, Fortune''s Best Workplaces in the Bay Area, and certified as a Great Place to Work!
Senior System and Manufacturing CoDesign Architect - Power, Thermal and Packaging NVIDIA CorpSenior System and Manufacturing CoDesign Architect - Power, Thermal and PackagingSanta Clara, CAWhat you'll be doing: Power, Thermal & Packaging Limits Analysis: Gather and analyze the hard constraints of packaging, power delivery, and thermal dissipation against roadmap demands, predicting when those constraints will reduce competitiveness and acting before they do. System-Manufacturing Co-Design: Drive improvements in product performance, performance-per-watt, and provisioning efficiency through system-manufacturing co-design, with the scope to follow the work wherever the highest-impact opportunities lead, whether that's power, thermal, or adjacent domains.
Senior Packaging Designer icreativesSenior Packaging DesignerRedwood City, CaliforniaRemoteIn this role, you'll lead packaging design efforts from the earliest concept to press-ready files, collaborating with clients and internal teams to deliver packaging that's visually compelling, strategically grounded, and production-ready. They're known for building standout brands through smart strategy, impactful visuals, and packaging that jumps off the shelf (in the best way possible).
Hardware Design Engineer - PCB Layout General MotorsHardware Design Engineer - PCB LayoutSunnyvale, CA$98,300–$177,800 / yearThe ECU hardware design team's mission is to ensure our products are designed to target the growing needs of our customers while ensuring robust, well-designed hardware which meets GM specifications and testing requirements from early hardware through the production design. The Role: In-vehicle electronics is a fast-growing technology in the global automotive industry featuring many cutting-edge technologies such as Compute, body controllers, multi-view cameras, Gig+Ethernet, PCIe, digital/analog interfaces and more.
Senior Hardware Design Engineer - PCB Design General MotorsSenior Hardware Design Engineer - PCB DesignSunnyvale, CA$106,600–$185,000 / yearPCB Layout Design Engineer would be responsible to develop various PCB layout designs for existing and new architecture-based ECUs, and collaborate with PCBA and ECAD engineers, run simulations, create PCB layouts, participate in design direction meetings, and create a collaborative environment with internal and external team members. The ECU hardware design team's mission is to ensure our products are designed to target the growing needs of our customers while ensuring robust, well-designed hardware which meets GM specifications and testing requirements from early hardware through the production design.
Sr. Signal and Power Integrity Engineer - SI/PI, Satellites Starlink Space Exploration Technologies CorpSr. Signal and Power Integrity Engineer - SI/PI, Satellites StarlinkPalo Alto, CAWork alongside RF engineers, antenna engineers, ASIC engineers, packaging engineers, mechanical engineers, thermal engineers, software engineers, supply chain, and production engineers (among others) to architect new products which will employ novel channels, interfaces, and power delivery strategies. As a Signal and Power Integrity Engineer on Starlink's Payload Engineering team, you'll have SI and PI ownership throughout the entire life-cycle of the portfolio of hardware that enables this connectivity, and sits at the intersection of electrical, mechanical, thermal analysis, software, and antenna/RF engineering.
Sr. SI/PI Engineer - Serdes, Satellites Starlink Space Exploration Technologies CorpSr. SI/PI Engineer - Serdes, Satellites StarlinkPalo Alto, CAWork alongside RF engineers, antenna engineers, ASIC engineers, packaging engineers, mechanical engineers, thermal engineers, software engineers, supply chain, and production engineers (among others) to architect new products which will employ novel channels, interfaces, and power delivery strategies. As a Signal and Power Integrity Engineer on Starlink's Payload Engineering team, you'll have SI and PI ownership throughout the entire life-cycle of the portfolio of hardware that enables this connectivity, and sits at the intersection of electrical, mechanical, thermal analysis, software, and antenna/RF engineering.
NewSignal Integrity Engineer - Serdes, Satellites Starlink Space Exploration Technologies CorpSignal Integrity Engineer - Serdes, Satellites StarlinkPalo Alto, CA$115,000–$155,000 / yearWork alongside RF engineers, antenna engineers, ASIC engineers, packaging engineers, mechanical engineers, thermal engineers, software engineers, supply chain, and production engineers (among others) to architect new products which will employ novel channels, interfaces, and power delivery strategies. As a Signal Integrity Engineer on Starlink's Payload Engineering team, you'll have SI ownership throughout the entire life-cycle of the portfolio of hardware that enables this connectivity, and sits at the intersection of electrical, mechanical, thermal analysis, software, and antenna/RF engineering.
Principal Signal and Power Integrity Engineer Microsoft CorpPrincipal Signal and Power Integrity EngineerMountain View, CA$142,800–$274,800 / yearRequired Qualifications: Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Masters Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. Drives the execution of architecture solutions across product lines or multiple product groups across teams that account for design trends and future concepts by leveraging cross- functional expertise, industry practices, and lessons learned from teams working across multiple product lines.
Principal Signal & Power Engineer (Die to Die and Chiplet Design) Microsoft CorpPrincipal Signal & Power Engineer (Die to Die and Chiplet Design)Mountain View, CA$142,800–$274,800 / yearDrives the execution of architecture solutions across product lines or multiple product groups across teams that account for design trends and future concepts by leveraging cross- functional expertise, industry best practices, and lessons learned from teams working across multiple product lines. IP design, voltage regulator, motherboard, CPU package, silicon, decoupling capacitor solutions, dielectric and copper loss, high-frequency discontinuities, timing budgets, power supply induced jitter, etc.) for data center processors and corresponding platforms to ensure optimized performance.
Senior Mechanical Hardware Engineer – ECU Connectors & Interfaces GMSenior Mechanical Hardware Engineer – ECU Connectors & InterfacesSunnyvale, California$125,200–$192,700 / yearCoordinate closely with electrical engineers and PCB designers on connector pinout constraints, PCB attachment strategy, soldering or alternate mounting concepts, grounding paths, shielding interfaces, and packaging of high-speed and power connections into complete electromechanical systems. Own mechanical design of connector-related content from concept through production release, including connector housings, integrated or discrete headers, terminal retention features, bus bar interfaces, seals, gaskets, and attachment features to the ECU housing.
Package Engineer Delos DataPackage EngineerPalo Alto, CaliforniaSelect and design optimal multi‑die package types (MCM, 2.5D, 3D, fan‑out, CoWoS, InFO, CPC, CPO) balancing electrical performance, thermal behavior, cost, and manufacturability. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.
Staff PCB Layout Design Engineer GMStaff PCB Layout Design EngineerSunnyvale, California$217,630–$245,000 / yearTen (10) years of experience as a Program Manager, Project Manager, Solution Architect, or related occupation Requires ten (10) years of experience with the following: Creating digital and analog HW PCB layout including HDI and high-power. Collaborate with test engineers to ensure that PCBA design is testable (Design for Test) and supports efficient testing processes.
Senior Mechanical Hardware Engineer - ECU Connectors & Interfaces General MotorsSenior Mechanical Hardware Engineer - ECU Connectors & InterfacesSunnyvale, CA$125,200–$192,700 / yearCoordinate closely with electrical engineers and PCB designers on connector pinout constraints, PCB attachment strategy, soldering or alternate mounting concepts, grounding paths, shielding interfaces, and packaging of high-speed and power connections into complete electromechanical systems. Own mechanical design of connector-related content from concept through production release, including connector housings, integrated or discrete headers, terminal retention features, bus bar interfaces, seals, gaskets, and attachment features to the ECU housing.
Staff PCB Layout Design Engineer General MotorsStaff PCB Layout Design EngineerMountain View, CA$217,630–$245,000 / yearTen (10) years of experience as a Program Manager, Project Manager, Solution Architect, or related occupation Requires ten (10) years of experience with the following: Creating digital and analog HW PCB layout including HDI and high-power. Collaborate with test engineers to ensure that PCBA design is testable (Design for Test) and supports efficient testing processes.
Senior Mechanical Design Engineer - ECU GMSenior Mechanical Design Engineer - ECUSunnyvale, California$125,200–$192,700 / yearOur Central Compute Hardware (CCH) Mechanical Design team is a dynamic, high-energy innovative group focused on developing enclosures for next‑generation ECUs (Electronic Control Units) commonly shared across both future ICE and EV vehicles manufactured by GM. Benefit options include medical, dental, vision, Health Savings Account, Flexible Spending Accounts, retirement savings plan, sickness and accident benefits, life insurance, paid vacation & holidays, tuition assistance programs, employee assistance program, GM vehicle discounts and more.
Staff Mechanical Hardware Engineer - ECU GMStaff Mechanical Hardware Engineer - ECUSunnyvale, California$159,400–$245,000 / yearOur CCH (Central Compute Hardware) Mechanical Design team is a dynamic, high-energy, and innovative group focused on developing enclosures for next generation ECUs (Electronic Control Units) commonly shared across both future ICE and EV vehicles manufactured by GM. Benefit options include medical, dental, vision, Health Savings Account, Flexible Spending Accounts, retirement savings plan, sickness and accident benefits, life insurance, paid vacation & holidays, tuition assistance programs, employee assistance program, GM vehicle discounts and more.
Product Development Engineer - Mechanical Design Amphenol HSIOProduct Development Engineer - Mechanical DesignSanta Clara, California$100,750–$168,870 / yearAmphenol High Speed Products Group is the market leader for high speed, high bandwidth electrical connectors for the Telecom/Datacom market (Mobile Networks, Storage, Servers, Routers, Switches, etc.). Amphenol Corporation is one of the world’s largest designers and manufacturers of electrical, electronic and fiber optic connectors and interconnect systems, antennas, sensors and sensor-based products and coaxial and high-speed specialty cable.
Contract Product Design FEA Engineer ICONMA, LLCContract Product Design FEA EngineerCupertino, CA$106.94–$111.94 / hourOur Client, a Consumer Products and Software Services company, is looking for a Contract Product Design FEA Engineer for their Cupertino, CA location. MS in Mechanical Engineering, Applied Mechanics, or similar discipline required along with 3+ years of relevant experience.
Senior Package Reliability Engineer Altera SemiconductorSenior Package Reliability EngineerSan Jose, California$166,900–$240,000 / yearWith more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. 8+ years of experience using thermal and thermomechanical simulation tools (e.g., Ansys, Abaqus, COMSOL, or equivalent) to develop and analyze warpage, coplanarity, stress, and deformation models for advanced semiconductor packages.
Advanced Package Design Engineer SKHYAAdvanced Package Design EngineerSan Jose, California$110,000–$155,000 / yearOur cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies.
Senior Laser & SOA Characterization Engineer LightmatterSenior Laser & SOA Characterization EngineerMountain View, CA$210,000–$267,000 / yearExperience operating optical and RF instruments, including laser current drivers, TEC controllers, OSAs, optical power meters, photodetectors, RF spectrum analyzers, oscilloscopes, bias tees, optical filters, polarization controllers, optical switches, and fiber-coupled components. In this role, you will lead advanced characterization, bring-up, validation, and root-cause analysis of semiconductor lasers, tunable laser sources, DFB lasers, external-cavity lasers, laser diodes, and semiconductor optical amplifiers.
Sr. Staff Engineer, Package and Interconnect Reliability Ayar LabsSr. Staff Engineer, Package and Interconnect ReliabilitySan Jose, CaliforniaYou will work closely with advanced foundry partners (including TSMC) to qualify advanced packaging technologies like COUPE (Compact Optical Engine), micro-bump/hybrid bonding, precision die attach, and critical optical-to-electrical interfaces such as Fiber Array Units (FAUs) and optical connectors. Failure Analysis & Physics of Failure (PoF) Root Cause Analysis: Drive deep-dive Failure Analysis (FA) on components that fail during reliability stress testing using advanced techniques (e.g., CSAM, High-resolution X-ray, SEM/EDX, FIB, and optical interferometry).
Senior Laser & SOA Characterization Engineer Lightmatter IncSenior Laser & SOA Characterization EngineerMountain View, CA$210,000–$267,000 / yearExperience operating optical and RF instruments, including laser current drivers, TEC controllers, OSAs, optical power meters, photodetectors, RF spectrum analyzers, oscilloscopes, bias tees, optical filters, polarization controllers, optical switches, and fiber-coupled components. In this role, you will lead advanced characterization, bring-up, validation, and root-cause analysis of semiconductor lasers, tunable laser sources, DFB lasers, external-cavity lasers, laser diodes, and semiconductor optical amplifiers.
Package Design Engineer - Staff Qualcomm IncPackage Design Engineer - StaffSanta Clara, CA$154,000–$252,800 / yearGeneral Summary: Qualcomm Data Center team is developing High performance, Energy efficient server solution for data center applications. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
Senior Mechanical Design Engineer - ECU General MotorsSenior Mechanical Design Engineer - ECUSunnyvale, CA$125,200–$192,700 / yearOur Central Compute Hardware (CCH) Mechanical Design team is a dynamic, high-energy innovative group focused on developing enclosures for next‑generation ECUs (Electronic Control Units) commonly shared across both future ICE and EV vehicles manufactured by GM. Benefit options include medical, dental, vision, Health Savings Account, Flexible Spending Accounts, retirement savings plan, sickness and accident benefits, life insurance, paid vacation & holidays, tuition assistance programs, employee assistance program, GM vehicle discounts and more.
Staff Mechanical Hardware Engineer - ECU General MotorsStaff Mechanical Hardware Engineer - ECUSunnyvale, CA$159,400–$245,000 / yearOur CCH (Central Compute Hardware) Mechanical Design team is a dynamic, high-energy, and innovative group focused on developing enclosures for next generation ECUs (Electronic Control Units) commonly shared across both future ICE and EV vehicles manufactured by GM. Benefit options include medical, dental, vision, Health Savings Account, Flexible Spending Accounts, retirement savings plan, sickness and accident benefits, life insurance, paid vacation & holidays, tuition assistance programs, employee assistance program, GM vehicle discounts and more.
NewExciting Opportunity for SI/PI Engineer_ Sunnyvale CA (Onsite only) Noblesoft TechnologiesExciting Opportunity for SI/PI Engineer_ Sunnyvale CA (Onsite only)Sunnyvale, CAIn this role, you will be responsible for signal integrity and power integrity analysis, modeling, and design optimization of next-generation multi-die packaging architectures including 2.5D/3D integration, silicon interposers, and high-bandwidth memory (HBM) interfaces. Perform time-domain simulations (eye diagram, BER analysis) for high-speed serial and parallel interfaces (PCIe Gen5/6, UCIe, HBM3/3E, DDR5, SerDes >112 Gbps).
Custom Characterization Engineer (Staff) Velaura AI IncCustom Characterization Engineer (Staff)San Jose, CAStaff / Principal)On-site - Full-timeBangaloreCustom DesignApplyCustom Characterization Engineer (Staff)On-site - Full-timeBangaloreApplyCustom Circuit Design (Sr. Manager)On-site - Full-timeBangalore / Santa Clara, CAApplyPhysical Design Engineer (Staff / Sr.
Physical Design Engineer (Staff / Sr. Staff / Principal) Velaura AI IncPhysical Design Engineer (Staff / Sr. Staff / Principal)San Jose, CAStaff / Principal)On-site - Full-timeBangaloreCustom DesignApplyCustom Characterization Engineer (Staff)On-site - Full-timeBangaloreApplyCustom Circuit Design (Sr. Manager)On-site - Full-timeBangalore / Santa Clara, CAApplyPhysical Design Engineer (Staff / Sr.