PCIe Silicon Validation & Debug Engineer Pyramid Consulting, IncPCIe Silicon Validation & Debug EngineerSunnyvale, CARemote$43–$47 / hourPCIe Engineer" OR "PCI Express Engineer" OR "Silicon Validation Engineer" OR "Validation Engineer" OR "Post Silicon Validation Engineer" OR "Pre Silicon Validation Engineer" OR "Silicon Debug Engineer") AND (PCIe OR "PCI Express") AND (Validation OR Verification OR Debug OR "Silicon Bring-up") AND (SystemVerilog OR UVM OR Python). Create directed and constrained-random tests targeting PCIe Transaction Layer (TLP), Data Link Layer (DLLP), and Physical Layer (PHY) functionality.
Senior Storage Engineer Microsoft CorpSenior Storage EngineerMountain View, CA$119,800–$234,700 / yearDoctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Masters Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Masters Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Principal Engineer, SCADA Engineering (BESS) Invenergy LLCPrincipal Engineer, SCADA Engineering (BESS)Oakland, CA$155,000–$180,000 / yearThis role is accountable for defining and documenting control strategies and data interfaces between substation devices, generation resources, data centers, remote operation centers, and external entities, and for driving reliable data connectivity and control readiness from design, commissioning, and turnover. Monitor construction progress remotely and via on site visits, support resolution of field issues, attend in person meetings with stakeholders, and provide on-site programming and field support during commissioning when required.
Sr NPI Engineer Nextracker Inc.Sr NPI EngineerFremont, CA$160,000–$175,000 / yearAt Nextpower, we are driving the global energy transition with an integrated clean energy technology platform that combines intelligent structural, electrical, and digital solutions for utility-scale power plants. Our talented worldwide teams are redefining how solar power plants are designed, built, and operated every day with smart technology, data-driven insights, and advanced automation.
Sr NPI Engineer Nextpower IncSr NPI EngineerFremont, CA$160,000–$175,000 / yearAt Nextpower, we are driving the global energy transition with an integrated clean energy technology platform that combines intelligent structural, electrical, and digital solutions for utility-scale power plants. Our talented worldwide teams are redefining how solar power plants are designed, built, and operated every day with smart technology, data-driven insights, and advanced automation.
CPU Implementation Lead Engineer Apple IncCPU Implementation Lead EngineerSanta Clara, CAWork with multi-functional engineering teams to implement and validate physical design in the aspects of timing, power, area, electrical analysis, functionality, reliability, and testability. Work extensively with the partition implementation team to make area/frequency/performance/power tradeoffs and remove bottlenecks in meeting design targets and delivery schedule.
Senior Control Systems Networking Engineer, Data Center Google LLCSenior Control Systems Networking Engineer, Data CenterSan Francisco, CAIdentify opportunities for continuous improvement and maturation of the OT environment to drive risk reduction, and serve as a technical liaison and collaborate between cross-functional teams to resolve complex design, integration, and deployment issues in mission-critical environments. Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Kirkland, WA, USA; Sunnyvale, CA, USA; Addison, TX, USA; New York, NY, USA; Reston, VA, USA; San Francisco, CA, USA; Austin, TX, USA; Atlanta, GA, USA.
Field Applications Engineer SolarEdgeField Applications EngineerSan Francisco, CASolarEdge proudly seeks to build a richly diverse workforce by hiring people with a diversity of thoughts, identities, perspectives, and experiences that help advance the difference we make for consumers, and by ensuring our people experience equity and inclusion in their work lives. At SolarEdge (NASDAQ: SEDG), we're a global leader in smart energy technology, with over 4,000 employees, offices in 34 countries, and millions of installations worldwide.
Reliability Design Engineer (Teradyne, San Jose, CA) Teradyne IncReliability Design Engineer (Teradyne, San Jose, CA)San Jose, CA$122,500–$196,000 / yearYou will help ensure products are ramp-ready by applying Teradyne's world-class Design for Reliability process, mitigating reliability risks early, driving rapid defect root-cause analysis and corrective action to accelerate product maturity, quality, and product reliability. The successful candidate will have minimum BSEE in Reliability Engineering, Mechanical Engineering, Electrical Engineering, or Industrial Engineering with 5 years or more reliability engineering experience in the design and manufacturing of electrical assemblies and systems engineering.
Robotics Powertrain Thermal Design Engineer, Thermal Engineering, Optimus Tesla IncRobotics Powertrain Thermal Design Engineer, Thermal Engineering, OptimusPalo Alto, CA$108,000–$264,000 / yearYou will work at the intersection of mechanical, electrical, and controls engineering, ensuring that actuators operate reliably across all mission profiles and duty cycles in a highly constrained form factor. Experience with thermal management of power electronics - PCB-level heat spreading, TIM selection, heatsink and housing interface design, junction temperature estimation.
Laser Engineer Lawrence Livermore National LaboratoryLaser EngineerLivermore, CA$175,530–$222,564 / yearPerform complex hands-on work activities on electro-optical components using techniques and methods to ensure optimal performance, which will include alignment, evaluation, calibration (offline and online), troubleshooting complex technical issues, data analysis (using computer-based data acquisition and controls), data archiving, and system documentation. In this critical role, you will be responsible for running and maintaining the advanced laser systems and support hardware for the world's largest laser with 192 beams, ensuring that all laser work is seamlessly planned, coordinated, and executed to support experiments in High Energy Density Physics, Laser Fusion and Ignition, and National Security.
Senior Test Engineer Penguin Solutions IncSenior Test EngineerNewark, CA$99,000–$134,000 / yearPenguin Solutions brings together differentiated infrastructure software, advanced memory, compute systems, end-to-end services, and industry-leading partner solutions in a full-stack AI factory platform designed to help customers deploy and scale AI workloads with speed and precision. The base pay range that the Company reasonably expects to pay for this position in California is $99,000 - $134,000; the pay ultimately offered may vary based on business considerations, including job-related knowledge, skills, experience, and education.
SoC Logic Design Engineer Intel CorpSoC Logic Design EngineerSanta Clara, CA$141,910–$200,340 / yearBachelor's degree in Electrical Engineering, Computer Engineering, or a related specialized field with 4+ years of hands-on experience in logic design, RTL development, and microarchitecture implementation, or Master's degree with 3+ years of experience in the same fields. This position resides within Intel's leading-edge silicon engineering group, which is dedicated to designing, developing, and scaling advanced semiconductor solutions for a wide range of applications.
Senior Embedded Software Application Engineer Alif Semiconductor, Inc.Senior Embedded Software Application EngineerPleasanton, CAWe are looking for self-driven and motivated Senior Application Engineer in Pleasanton, CA to help us promote and support the groundbreaking family of Ensemble Micro Controllers that has received a lot of industry attention. This policy applies to all terms and conditions of employment, including recruiting, hiring, placement, promotion, termination, layoff, recall, transfer, leaves of absence, compensation, and training.
Senior IC Packaging Engineer Axiado CorpSenior IC Packaging EngineerSan Jose, CAAxiado has also won numerous industry awards for our ground-breaking products and technological innovations, including being named one of Fast Companys 2025 Top 10 Most Innovative Companies in Security, winning the 2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliances 2025 Start-Up to Watch award. We are a fast-growing, well funded silicon, systems, and solutions company pioneering a new category of semiconductor called the Trusted Control/Compute Unit (TCU) that combines advanced hardware security, AI driven resilience and efficiency, and real-time platform management.
Sr. ASIC EDA Workflow Engineer Recogni IncSr. ASIC EDA Workflow EngineerSunnyvale, CAAs a valued senior member of our ASIC team, you will guide and assist your colleagues to help improve and invent EDA workflows within a fast-paced, agile HPC development environment that utilizes EDA tools from external companies like Cadence and as well as internally developed workflows. What you'll bring: Experience leading the development and support for compilation, build automation, testing, packaging and installation project generators that build object files like either CMake, GNU make, and/or Ninja, as well as experience with CI/CD and modern Git Branching workflows.
Principal Hardware Engineer / Director of Hardware Arable Labs, Inc.Principal Hardware Engineer / Director of HardwareSan Francisco, CAProvide technical leadership and mentorship, helping to influence technology direction and build long-term organizational capability. We are seeking a senior hardware leader to spearhead the development of our hardware ecosystem, including the Arable Mark 3 and future sensing platforms.
Staff Engineer, Optics and RF Cowboy SpaceStaff Engineer, Optics and RFSan Carlos, CaliforniaOur satellites operate in Low Earth Orbit to collect sunlight and enable a new class of capabilities—from powering on-orbit compute, to transmitting energy via infrared lasers (space-to-earth and space-to-space), powering on-orbit compute to delivering secure, high-bandwidth optical data. This role is heavily focused on board-level RF design and integration, working closely with electrical, PCB layout, firmware, and test engineers to deliver high-performance RF subsystems capable of operating reliably in the space environment.
Firmware Engineer Cowboy SpaceFirmware EngineerSan Carlos, California$130,000–$185,000 / yearOur satellites operate in Low Earth Orbit to collect sunlight and enable a new class of capabilities—from powering on-orbit compute, to transmitting energy via infrared lasers (space-to-earth and space-to-space), powering on-orbit compute to delivering secure, high-bandwidth optical data. Export Control Requirement: To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR), applicants must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.
RF Integration Engineer (6202) itD TechRF Integration Engineer (6202)San Jose, California$27–$27.69 / hourOperate and troubleshoot RF test and measurement equipment, including network analyzers, spectrum analyzers, vector signal analyzers/generators, power meters, traffic generators, and wireless sniffers. Collaborate with Hardware Engineering, Software Engineering, Product Management, Supply Chain, and Compliance teams to support product development and validation efforts.
Integration RTL Design Engineer Advanced Micro Devices, IncIntegration RTL Design EngineerSan Jose, CaliforniaFull ASIC Development Lifecycle: Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation. RTL Design & Microarchitecture: Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets and timing requirements.
Packaging Design Engineer Advanced Micro Devices, IncPackaging Design EngineerSan Jose, CaliforniaThis role requires good communication skills to work with other teams and engineers at the various design centers to carry the projects from design start to signoff stages. The AECG - Embedded Team builds and optimizes platforms for embedded and commercial applications, working across silicon, firmware, and software to deliver reliable, high‑performance solutions at scale.
RTL Tools & Methodology Engineer Advanced Micro Devices, IncRTL Tools & Methodology EngineerSan Jose, CaliforniaYou are comfortable working on a small, highly capable team where initiative and ownership are valued, and you enjoy collaborating with design and verification teams to continuously improve engineering processes. Collaborate with the design team to drive continuous improvements in front-end design methodologies, ensuring top-quality RTL across areas such as Lint, CDC, formal equivalence, and low-power verification.
SerDes RTL Design Engineer Advanced Micro Devices, IncSerDes RTL Design EngineerSan Jose, CaliforniaAMD SerDes Technology team is searching for a passionate and innovative RTL design engineer to develop high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives.
Systems Application Engineer Advanced Micro Devices, IncSystems Application EngineerSanta Clara, CaliforniaIn this customer-centric role, you will collaborate with external OEM partners, internal development and validation teams, and cross-functional stakeholders to bring next-generation server platforms to market powered by AMD’s Instinct Accelerators—and ensure their successful deployment in customer data centers. Join AMD’s Datacenter GPU Platform Application Engineering team as a System Application Engineer, supporting our Data Center GPU customers across Cloud, HPC, and OEM segments.
EMC Design & Test Engineer (Teradyne, San Jose, CA) Teradyne, Inc.EMC Design & Test Engineer (Teradyne, San Jose, CA)San Jose, CA$122,500–$196,000 / yearInterpret and perform EMC test methods including Radiated Emissions, Conducted Emissions, ESD, Radiated Immunity, EFT/Burst, Surge, Conducted Immunity, Magnetic Field Immunity, Voltage Dips/Interrupts, Harmonics, and Flicker. Bachelor's degree in Electrical or Electronics Engineering or Physics; or equivalent combined experience and education - which would include an associate's degree or technical school certification or related military training in electronics.
Ai/Ml Physical Design Flow Engineer TenstorrentAi/Ml Physical Design Flow EngineerSanta Clara, CATenstorrent is seeking an Physical Design Engineer to lead cross-functional efforts to solve complex physical design challenges and develop end-to-end RTL-to-GDS methodologies across advanced nodes, with a strong focus on PPA and runtime improvements. The engineer will architect, integrate, and deploy AI/ML-driven solutions into production physical design flows, creating custom CAD tools and partnering with internal teams and EDA vendors to drive next-generation, ML-enabled capabilities.
Senior Formal Verification Engineer - AI Soc Development Intel Corp.Senior Formal Verification Engineer - AI Soc DevelopmentSanta Clara, CA$220,920–$311,890 / yearHarnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. As a Senior Formal Verification Engineer, you will play a critical role in ensuring the functional correctness of complex digital designs using advanced formal methods.
Lead Android Platform Engineer LogitechLead Android Platform EngineerSan Jose, California$168,000–$240,000 / yearLogitech also offers Wellness Programs, Health Savings Account Plans, access to Expert Medical Opinions, Identity Theft Protection, Breast Milk Delivery to Nursing Mothers on Business Travel, access to a Group Legal Plan, Donations Matching Programs, Employee Product Discounts, and access to Auto, Home, and Pet Insurance. The candidate should also have deep domain knowledge in at least one major Android subsystem such as the Camera Framework, Display Framework, or Audio Framework , with the ability to work across multiple subsystems as needed.
Soc Logic Design Engineer Intel Corp.Soc Logic Design EngineerSanta Clara, CA$141,910–$200,340 / yearBachelor's degree in Electrical Engineering, Computer Engineering, or a related specialized field with 4+ years of hands-on experience in logic design, RTL development, and microarchitecture implementation, or Master's degree with 3+ years of experience in the same fields. This position resides within Intel's leading-edge silicon engineering group, which is dedicated to designing, developing, and scaling advanced semiconductor solutions for a wide range of applications.
Sr. Logic Design Engineer Intel Corp.Sr. Logic Design EngineerSanta Clara, CA$141,910–$200,340 / yearMinimum Qualifications: Candidate must possess a Bachelor's degree in Electrical or Computer Engineering or a related field and 4+ years' experience OR a Master's degree in Electrical or Computer Engineering or a related field and 2+ years' experience OR a PhD in Electrical or Computer Engineering or a related field and 1+ years' experience. Job Details: Job Description: Intel's HIPD team is looking for an experienced senior Logic design engineer to join the rapidly growing UCIE PHY IP for Intel's flagship datacenter/server designs.
Lead Analog Serdes Architect/Design Engineer Intel Corp.Lead Analog Serdes Architect/Design EngineerSanta Clara, CA$220,920–$311,890 / yearThe ideal candidate should have a minimum of MS in Electrical Engineering with 8+ years of experience in high-speed serial links and deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership.
Mixed Signal Logic Design Engineer Intel Corp.Mixed Signal Logic Design EngineerSan Jose, CA$122,440–$232,190 / yearApplies various strategies, tools, and methods for mixed signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Job Details: Job Description: Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or highspeed IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Senior Design Verification Engineer Intel CorpSenior Design Verification EngineerSanta Clara, CA$164,470–$311,890 / yearAdditional Locations: Business group: The Central Engineering Group (CEG) is Intel''s data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). Experience in interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; cache coherency and memory consistency models.
Principal Engineer, AMS IP Architecture Intel CorpPrincipal Engineer, AMS IP ArchitectureSanta Clara, CA$220,920–$311,890 / yearD. in Electrical Engineering, Computer Engineering, or a related field with focus on high-speed communications, analog circuits, or signal processing • Deep expertise in one or more of the following: SerDes modeling in MATLAB or Simulink, high-speed analog CMOS design, DSP techniques for SerDes equalization and timing recovery, or communications theory including equalization, coding, and noise filtering • Experience analyzing and closing link budgets for NRZ or PAM4 signaling at 100Gbps or higher, accounting for transmitter impairments, channel loss, reflection, crosstalk, and receiver noise • Hands-on work with SerDes transmitter and receiver architectures, equalization techniques such as FFE, DFE, and CTLE, or CDR loop dynamics and jitter tolerance • Ability to correlate models with silicon measurements, debug discrepancies systematically, and update models to reflect real-world behavior • Familiarity with C, Verilog-A, or SystemVerilog for co-simulation or algorithm prototyping is a plus. Business group: The Central Engineering Group (CEG) is Intel''s data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies).
Sr. Staff ASIC Verification Engineer Recogni IncSr. Staff ASIC Verification EngineerSunnyvale, CAResponsibilities: Your responsibilities will be wide-ranging and and run the gamut of working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular SystemVerilog and UVM, handling bug tracking and coverage convergence and developing scripts and methodologies for the front-end ASIC flow. This ASIC's design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to deliver the high-performance multi-chip silicon solutions that are at the heart of Tensordyne's vertically integrated, generative AI inference acceleration systems for data centers.
Hardware Infrastructure & CI/CD Engineer EfficientAI CorpHardware Infrastructure & CI/CD EngineerSan Jose, CA$180,000–$220,000 / yearThe ideal candidate must be a full-stack infrastructure engineer who is equally comfortable writing Go services, managing Kubernetes environments, debugging low-level test programs, and working with a wide variety of embedded hardware such as FPGA, Ambiq, Apollo, PIC32 and Efficient E1. ATLAS supports automated benchmarking and validation of both our company''s products and competitor hardware, providing essential data that drives engineering and product decisions.
EMC Design & Test Engineer (TERADYNE, San Jose, CA) Teradyne IncEMC Design & Test Engineer (TERADYNE, San Jose, CA)San Jose, CA$122,500–$196,000 / yearInterpret and perform EMC test methods including Radiated Emissions, Conducted Emissions, ESD, Radiated Immunity, EFT/Burst, Surge, Conducted Immunity, Magnetic Field Immunity, Voltage Dips/Interrupts, Harmonics, and Flicker. Bachelor's degree in Electrical or Electronics Engineering or Physics; or equivalent combined experience and education - which would include an associate's degree or technical school certification or related military training in electronics.
Performance Library Engineer EfficientAI CorpPerformance Library EngineerSan Jose, CA$130,000–$230,000 / yearIn this role, you will take ownership of complex, performance-critical, library development while working closely with Efficient's compiler and embedded teams providing direct feedback on compiler enhancements and performance related tools. Efficient's Performance Library Engineers create and optimize libraries and frameworks that are used by customers of the world's most energy-efficient programmable processor (the "Fabric").
Performance Research Engineer multiple levels EfficientAI CorpPerformance Research Engineer multiple levelsSan Jose, CA$180,000–$250,000 / yearEfficient's Performance Research Engineers research new optimization techniques; design new tools for AI assisted optimization and performance analysis; collaborate with our architecture team on the design of future hardware; design and perform modeling experiments using our architecture simulator; and collaborate with our world class compiler team, evaluating code-generation quality, suggesting new intrinsics, influencing the ISA, and experimenting with new language extensions. Excellent written, verbal, analytical and technical communication skills, with the ability to clearly document complex systems, lead discussions across teams, as well as the ability to drive consensus across teams.
RTL Design Engineer Advanced Micro Devices IncRTL Design EngineerSan Jose, CAKEY RESPONSIBILITIES: RTL Design & Microarchitecture: Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets and timing requirements. Full ASIC Development Lifecycle: Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation.
Sr. ASIC Verification Engineer Recogni IncSr. ASIC Verification EngineerSunnyvale, CAResponsibilities: Your responsibilities will be wide-ranging and and run the gamut of working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular SystemVerilog and UVM, handling bug tracking and coverage convergence and developing scripts and methodologies for the front-end ASIC flow. This ASIC's design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to deliver the high-performance multi-chip silicon solutions that are at the heart of Tensordyne's vertically integrated, generative AI inference acceleration systems for data centers.
Senior RTL Design Engineer Advanced Micro Devices IncSenior RTL Design EngineerSan Jose, CAKEY RESPONSIBILITIES: RTL Design & Microarchitecture: Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets and timing requirements. Full ASIC Development Lifecycle: Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation.
Principal Product Engineer Cadence Design Systems IncPrincipal Product EngineerSan Jose, CA$136,500–$253,500 / yearJob responsibilities: Perform Product Engineering work for Genus Synthesis Solution (Genus), a logic synthesis software used for synthesizing a design described in a high-level language into logic gates, to achieve best-in-class Power, Performance & Area (PPA) for latest digital ASICs. Experience in Logic Design and Synthesis, Formal Verification, Low Power design, Physical Design and Timing Closure for block level and top level designs.
Systems Application Engineer- (Mandarin) Advanced Micro Devices IncSystems Application Engineer- (Mandarin)Santa Clara, CAIn this customer-centric role, you will collaborate with external OEM partners, internal development and validation teams, and cross-functional stakeholders to bring next-generation server platforms to market powered by AMD's Instinct Accelerators-and ensure their successful deployment in customer data centers. THE ROLE: Join AMD's Datacenter GPU Platform Application Engineering team as a System Application Engineer, supporting our Data Center GPU customers across Cloud, HPC, and OEM segments.
System Software Engineer, Networking Recogni IncSystem Software Engineer, NetworkingSunnyvale, CADrive route, neighbor, next-hop, and ECMP programming flows from control-plane intent all the way to confirmed ASIC hardware state, and build mechanisms that distinguish control-plane acceptance from SDK acceptance from hardware programming acknowledgement. This is a deeply technical, hands-on role for someone who is at home moving up and down the stack - tuning userspace services, patching kernel drivers, and reaching into firmware - to squeeze latency, bandwidth, and reliability out of large, lossless networks.
NewStaff QA Engineer - Cinema Imaging Dolby Laboratories IncStaff QA Engineer - Cinema ImagingSan Francisco, CA$152,900–$210,200 / yearExperience with Digital Cinema technologies and workflows such as DCP, MXF, JPEG 2000, Dolby Vision, HDR, DCI color workflows, cinema servers, integrated media blocks, projection systems, 3D, or multi-projector systems. Proven experience of implementing and maintaining scalable and reusable Python based test automation frameworks/tools/tests using various tools/libraries like Pytest, Selenium, etc using Python.
Field Application Engineer MKIS Professional SearchField Application EngineerSanta Clara, CaliforniaOur client is a global leader in low-power, short-range wireless connectivity semiconductor solutions , consistently ranked as a top vendor in the BLE (Bluetooth Low Energy) space. With a strong portfolio of customer design wins and a robust product roadmap, we are helping to expand the technical support team to accelerate growth across key markets.
NewFounding Music AI Engineer David Joseph & CompanyFounding Music AI EngineerSan Francisco, California$175,000–$225,000 / yearIt's a small, close-knit team pairing deep ML research talent with consumer product builders, and this is a genuine ground-floor opportunity where each early hire shapes both the product and the culture. Our client is hiring a founding engineer to help build production-ready ML systems that power the next generation of music learning for a large and growing base of musicians.
NewEmbedded Software Engineer - Labs, DoorDash Air DoorDash IncEmbedded Software Engineer - Labs, DoorDash AirSan Francisco, CA$159,800–$235,000 / yearWe value a diverse workforce - people who identify as women, non-binary or gender non-conforming, LGBTQIA+, American Indian or Native Alaskan, Black or African American, Hispanic or Latinx, Native Hawaiian or Other Pacific Islander, differently-abled, caretakers and parents, and veterans are strongly encouraged to apply. At DoorDash, our mission to empower local economies shapes how our team members move quickly, learn, and reiterate in order to make impactful decisions that display empathy for our range of users-from Dashers to merchant partners to consumers.