UNKNOWN

FEED

The ideal candidate will have a proven track record of completing multiple successful ASIC design and verification cycles-from architecting testbenches (networking background preferred) to achieving full verification closure. As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.

Broadcom Inc

R&D Engineer IC Design 5

This position involves working with the latest technology to continue driving next generation AI/ML ecosystems through our PCIe Switch Products - and managing mega datacenters, while leading world class performance, through our Enterprise Storage Products. As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.

Broadcom Corporation

Physical Design Engineer

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This position involves working with the latest technology to continue driving next generation Artificial Intelligence and Machine Learning ecosystems through our PCIe Switch Products - and managing mega datacenters, while leading world class performance, through our Enterprise Storage Products. As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth.

Physical IC Design Engineer

We are looking for a motivated and astute individual to join our team as a logic design engineer.as a logic design engineer you will use your knowledge of specifications, mathematics, and computation to write efficient and elegant rtl for implementing components of complex networking asics. Job Description: The core switch group (csg) at broadcom focused on developing high-performance ethernet switch silicon and software, primarily targeting hyperscale data centers, cloud providers, and enterprise networks.

R&D Digital Design Engineer

Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.

Visualize your future . . . We Do 
NVIDIA is the world leader in graphics processing technologies, creating innovative, industry-changing products for computing, consumer electronics, and mobile devices. NVIDIA products are transforming visually-rich applications such as video games, film production, broadcasting, industrial design, space exploration, and medical imaging. We invest in our people and our technologies, support and fund industry research around the world, and consistently deliver high-quality products. NVIDIA's culture promotes and inspires a team of world-class employees to be at the top of their game. We've created an environment where talents are recognized and collaboration is valued. Our employees are shaping the world of tomorrow. . . today. We invite you to explore the opportunities available at NVIDIA to see what your future may hold.

NVIDIA Corp

Senior ASIC Design Engineer - Clocks IP

RESPONSIBILITIES: Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts. Job Description: Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs.

Package Design Engineer

and/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing, vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training. Required for Certain Job Profiles: Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10,001 lbs.

YEAR

Blue Origin Enterprises LP

Principal Modem PHY IP Design Engineer - Terawave

Principal Modem PHY IP Design Verification Engineer - Terawave

Demonstrated experience applying AI/ML techniques in engineering workflows - this could include using LLMs for code generation and debugging, building ML-assisted design analysis tools, or integrating AI-assisted flows into EDA environments. This role is a rare opportunity to craft production-grade EDA tooling that operates at the bleeding edge of packaging technology, where no commercial solution exists yet and the problems you solve become the new industry baseline.

Package Design Methodology Engineer

In this position, you will get the chance to build complex chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

CPU Design Methodology Engineer

Work closely with sw & customer teams on high pressure escalations from the field, including reading logs, identifying the bug, determining the best fix with minimal interruption to the field, delivering the final solution, determining if any other systems are susceptible, and implementing measures to prevent the issue from occurring again. Working closely with cross-functional teams including software, product management, and manufacturing, our engineers innovate on system architectures, high-speed PCB designs, and signal integrity to deliver state-of-the-art products that drive network performance and reliability.

Arista Networks, Inc.

Hardware Design Integrity Engineer

As a Senior SOC Design Engineer, you'll work at the forefront of technology, integrating advanced ASICs, and partnering with experts in ASIC design, Physical design, CAD, Package Design, Software, DFT, and more. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.

Nvidia

Senior SOC Design Engineer

What you'll be doing: Working closely with product design engineers, you'll perform PCB layout of high speed/high-density value-conscious PCBs for all business units at NVIDIA (Information Network, GPU Desktop, Notebook, Automotive, Professional, Data Center, Deep Learning, and AI). We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our exclusive engineering teams are rapidly growing.

PCB Design Layout Engineer

Hands-on experience with sensors, power electronics (high voltage, high power, AC, SMPS, LDO), processing (MCU, MPU, SOM), networking (Ethernet, CAN-FD, isoSPI), on board communication (SPI, UART, I2C, JTAG), data acquisition (IO, ADC, DAC), and control systems (gate drivers, motor drivers, HSD). What you'll bring: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 7+ years of relevant experience (battery or energy storage systems experience is a plus); OR Master's degree with 5+ years of relevant experience.

Form Energy

Staff Electrical Engineer, PCB Design

ASIC Design Engineer - Clocks IP

This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing you to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What you will be doing: Working with architects, design leads, physical design leads and package leads, you will develop and to craft and optimize floorplans during early chip development.

ASIC Floorplan Design Engineer - New College Grad 2026

What you'll be doing: As a Senior ASIC Design Engineer at NVIDIA, you will be essential in documenting, implementing, and delivering fully verified, high-performance, area- and power-efficient RTL to meet design goals and specifications. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Circuit Design Engineer Jobs in Palo Alto, CA

R&D Engineer IC Design 5 Broadcom Inc

Physical Design Engineer Broadcom Corporation

Physical IC Design Engineer Broadcom Corporation

Physical IC Design Engineer Broadcom Inc

R&D Digital Design Engineer Broadcom Corporation

Senior ASIC Design Engineer - Clocks IP NVIDIA Corp

Package Design Engineer Broadcom Inc

Principal Modem PHY IP Design Engineer - Terawave Blue Origin Enterprises LP

Principal Modem PHY IP Design Verification Engineer - Terawave Blue Origin Enterprises LP

Package Design Methodology Engineer NVIDIA Corp

Package Design Engineer Broadcom Corporation

CPU Design Methodology Engineer NVIDIA Corp

Hardware Design Integrity Engineer Arista Networks, Inc.

Senior SOC Design Engineer Nvidia

PCB Design Layout Engineer Nvidia

Staff Electrical Engineer, PCB Design Form Energy

ASIC Design Engineer - Clocks IP NVIDIA Corp

Physical Design Engineer Broadcom Inc

ASIC Floorplan Design Engineer - New College Grad 2026 NVIDIA Corp

Senior ASIC Design Engineer NVIDIA Corp

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