ASIC Design Verification Emulation Engineer Cisco Systems IncASIC Design Verification Emulation EngineerSan Jose, CA$165,000–$241,400 / yearCisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. For quota-based incentive pay, Cisco typically pays as follows: 75% of incentive target for each 1% of revenue attainment up to 50% of quota 1.5% of incentive target for each 1% of attainment between 50% and 75% 1% of incentive target for each 1% of attainment between 75% and 100%.
ASIC Design Engineer, STA Cisco Systems IncASIC Design Engineer, STASan Jose, CA$152,500–$219,200 / yearCisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. As an ASIC Design Engineer on the STA team, you will play a pivotal role in extraction and static timing analysis (STA) flow development, convergence strategies, and correlation between PNR, Spice, and STA, while working alongside the Physical Design team.
RTL Design Engineer Etched.ai IncRTL Design EngineerSan Jose, CABenefits Medical, dental, and vision packages with generous premium coverage $500 per month credit for waiving medical benefits Housing subsidy of $2k per month for those living within walking distance of the office Relocation support for those moving to San Jose (Santana Row) Various wellness benefits covering fitness, mental health, and more Daily lunch + dinner in our office. Strong candidates may also have experience with (Nice-to-have qualifications) • Experience with PCIe, Ethernet, or HBM technologies • Familiarity with transformer models and machine learning • Familiarity with numerical representations and functions • Ability to program with Python or another scripting language.
ASIC Design Verification Engineer, Technical Leader Cisco Systems IncASIC Design Verification Engineer, Technical LeaderSan Jose, CA$183,800–$263,600 / yearWho We Are: The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. For quota-based incentive pay, Cisco typically pays as follows: 75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and.
Design Verification Engineer - Interface IP Etched.ai IncDesign Verification Engineer - Interface IPSan Jose, CAKey Responsibilities • End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors • Understand vendor IP configurations and handle handshake with internal IP team • Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications • Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture • Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios. Benefits • Medical, dental, and vision packages with generous premium coverage • $500 per month credit for waiving medical benefits • Housing subsidy of $2k per month for those living within walking distance of the office • Relocation support for those moving to San Jose (Santana Row) • Various wellness benefits covering fitness, mental health, and more • Daily lunch + dinner in our office.
Sr. ASIC Design Verification Engineer Cisco Systems IncSr. ASIC Design Verification EngineerSan Jose, CA$165,000–$241,400 / yearCollaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration Ensure comprehensive verification coverage through code and functional coverage implementation and review Minimum Qualifications: Bachelor''s degree in electrical/computer science/computer engineering/related degree and 7+ years of related experience or Master''s in electrical/computer science/computer engineering/related degree and 4+ years of related experience, or PhD in electrical/computer science/computer engineering/related degree + 1 year of related experience. The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $165,000.00 - $277,600.00 Non-Metro New York state & Washington state: $146,700.00 - $247,000.00 * For quota-based sales roles on Cisco's sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.
Design Verification Engineer - Internal IP Etched.ai IncDesign Verification Engineer - Internal IPSan Jose, CABenefits Medical, dental, and vision packages with generous premium coverage $500 per month credit for waiving medical benefits Housing subsidy of $2k per month for those living within walking distance of the office Relocation support for those moving to San Jose (Santana Row) Various wellness benefits covering fitness, mental health, and more Daily lunch + dinner in our office. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.
Sr Networking Hardware Design Engineer Cisco SystemsSr Networking Hardware Design EngineerSan Jose, California$152,400–$221,800 / yearThe applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $152,400.00 - $255,100.00 Non-Metro New York state & Washington state: $134,300.00 - $224,800.00 * For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined. Join the Cisco Low End Enterprise and Small Business switch team in developing the next generation switches for simplified and easy-to-use cloud connected edge Networks customers.
NewElectrical Design Validation Engineer MetaElectrical Design Validation EngineerSunnyvale, CASummaryThe Meta Hardware Validation Engineer will play a crucial role in ensuring the quality and performance of Meta's hardware products. This position involves designing, executing, and analyzing comprehensive validation plans to guarantee that Meta's hardware meets product requirements.
NewElectrical Design and Analysis Engineer 4 The Structures CompanyElectrical Design and Analysis Engineer 4Mountain View, CAAs trusted partners to leading aerospace and defense OEMs and Tier 1 suppliers, we connect professionals with career opportunities to grow and excel in aviation, aerospace, and defense. Uses scripting including Python, Perl, and Make and revision control including git and svn to automate flows.
Staff Electrical Engineer – Test Systems E-SpaceStaff Electrical Engineer – Test SystemsSaratoga, CAYou will work collaboratively with engineers of various disciplines to develop the automated test framework for satellite avionics and systems including test methods, custom PCBAs, harnesses, and other hardware, and ultimately support the rigorous flight-like testing of satellite hardware. Our team members have a strong sense of dedication and responsibility; this includes a strong commitment to our mission to create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet.
Digital - Principal Systems/DSP Engineer Eliyan CorporationDigital - Principal Systems/DSP EngineerCAAs the Principal Systems/DSP Engineer at Eliyan, you will define and drive the DSP architecture for next-generation 224G and 448G SerDes designs powering tomorrow's chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. • Architect and evaluate clock and data recovery (CDR) algorithms and loop dynamics, including jitter tolerance analysis, bang-bang and linear CDR trade-offs, and frequency acquisition strategies.
Analog IC Layout Engineer Neuralink CorpAnalog IC Layout EngineerFremont, CA$83,000–$139,000 / yearJob Description and Responsibilities: We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces.
Vice President of Engineering - Optical Circuit Switch (OCS) II-VI Optical Systems, Inc.Vice President of Engineering - Optical Circuit Switch (OCS)Sunnyvale, CAWe are a vertically integrated manufacturing company that develops innovative products for diversified applications in the industrial, optical communications, military, life sciences, semiconductor equipment, and consumer markets. Coherent provides a comprehensive career development platform within an environment that challenges employees to perform at their best, while rewarding excellence and hard-work through a competitive compensation program.
Supplier Quality Engineer 2 Mattson Technology IncSupplier Quality Engineer 2Fremont, CAParticipates on cross functional teams during field excursions, drawing from expertise of others and his/her own to support failure analysis, establish root cause, implement corrective action, validate the effectiveness of the applied solutions and implementation and driving corrective actions across the manufacturing, design and supply chain. Collaborates cross functionally with the NPI team, develops product performance, reliability, durability test plans during development, Alpha and Beta phases and during the product life cycle ensure the product meets its intended design and specifications.
Director - AI Research and Engineering Efficiency (Circuit Platform) Cisco Systems IncDirector - AI Research and Engineering Efficiency (Circuit Platform)San Jose, CA$291,500–$369,100 / yearYou will be measured on your ability to drive tangible improvements in AI productivity (hours saved, workflow cycle-time reduction), agent reliability (task completion rates, reduction in human overrides), model quality (groundedness, hallucination reduction), inference economics (cost per successful task, GPU utilization), and developer velocity (time-to-production, evaluation coverage). You will define Cisco-scale agentic system architecture, including planning, tool execution, agent-to-agent handoffs, memory, persistent state, human approval, policy enforcement, secure tool access, observability, and failure recovery.
Senior BMS Electrical Engineer Archer Aviation IncSenior BMS Electrical EngineerSan Jose, CA$144,000–$180,000 / yearArcher is an aerospace company based in San Jose, California building an all-electric vertical takeoff and landing aircraft with a mission to advance the benefits of sustainable air mobility. Our sights are set high and our problems are hard, and we believe that diversity in the workplace is what makes us smarter, drives better insights, and will ultimately lift us all to success.
NewElectrical Engineer 4 Lam ResearchElectrical Engineer 4Fremont, CA$104,000–$231,000 / yearElectrical Engineers design equipment with the following subsystems: Heater control (PID Control, loop dynamics, tuning parameters), pressure control, 3‑phase power delivery, DC power delivery, cable harness development, analog control, digital control, EtherCAT, RS232, embedded controls, RF power delivery, filter development, integration of motion control, safety certification, and creation of software functional specifications. Knowledgeable in CAD tools for circuit design and simulation (e.g., PCAD, ORCAD, Zuken, AutoCAD, Spice, ADS, HFSS).Preferred QualificationsAbility to define functional requirements and execute in a dynamic team environment.
Power Electronics Engineer E-SpacePower Electronics EngineerSaratoga, CAWe’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life. Our team members have a strong sense of dedication and responsibility; this includes a strong commitment to our mission to create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet.
Staff Satellite RF Electrical Engineer E-SpaceStaff Satellite RF Electrical EngineerSaratoga, CA$120,000–$200,000 / yearWe are redefining how satellites are designed, manufactured and used—so we’re looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in-orbit activities. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.
Senior BMS Electrical Engineer Archer AviationSenior BMS Electrical EngineerSan Jose, CA$144,000–$185,000 / yearArcher is an aerospace company based in San Jose, California building an all-electric vertical takeoff and landing aircraft with a mission to advance the benefits of sustainable air mobility. Our sights are set high and our problems are hard, and we believe that diversity in the workplace is what makes us smarter, drives better insights, and will ultimately lift us all to success.
DFT (Design For Test) Engineer EtchedDFT (Design For Test) EngineerSan Jose, CaliforniaDevelop and implement robust Design for Test (DFT) architectures for ASIC and SoC designs to enhance test coverage, debug capability, and fault isolation. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Senior/Staff Electrical Systems Engineer PDF Solutions IncSenior/Staff Electrical Systems EngineerMilpitas, CA$130,000–$170,000 / yearDrive Design for Reliability (DfR) for eProbe: Implement advanced DfR methodologies to proactively mitigate potential failure modes for various electrical subsystems of eProbe, including but not limited to AC/DC power distribution, high-voltage power supplies, e-beam column control and detection electronics, motion control electronics, high vacuum electronics, etc. This Electrical Systems Engineer role focuses on electrical system reliability and performance, supply chain, managing electrical system performance, uptime, and component logistics for eProbe Tools, balancing design/component reliability with procurement, scheduling, and supplier management for critical electrical parts, ensuring high availability and efficient delivery for manufacturing/service.
ASIC DFT Engineer Broadcom IncASIC DFT EngineerSan Jose, CA$141,300–$226,000 / yearValidating & Debugging Test vectors on ATE during the silicon bring up phase • Assisting with silicon failure analysis, diagnostics & yield improvement efforts • Interfacing with the customer, physical design and test engineering/manufacturing teams located globally • Working closely with I/P DFT engineers & other stakeholders • Debugging customer returned parts on the ATE • Innovating newer DFT solutions to solve testability problems in 3nm & beyond • Automating DFT & Test Vector Generation flows. Responsibilities: • Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC • Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration • Responsibilities includes pattern generation & Verification at chip level, Rapid bring-up at ATE and RMA support • Working closely with STA and DI Engineers design closure for test • Generating, Verifying & Debugging Test vectors before tape release.
Senior Electrical Systems Engineer PDF SolutionsSenior Electrical Systems EngineerMilpitas, California$130,000–$170,000 / yearFull timeDrive Design for Reliability (DfR) for eProbe®: Implement advanced DfR methodologies to proactively mitigate potential failure modes for various electrical subsystems of eProbe®, including but not limited to AC/DC power distribution, high-voltage power supplies, e-beam column control and detection electronics, motion control electronics, high vacuum electronics, etc. This Electrical Systems Engineer role focuses on electrical system reliability & supply chain, managing electrical system performance, uptime, and component logistics for eProbe® Tools, balancing design/component reliability with procurement, scheduling, and supplier management for critical electrical parts, ensuring high availability and efficient delivery for manufacturing/service.
Principal Engineer, SerDes AMS Design and Architecture Ayar LabsPrincipal Engineer, SerDes AMS Design and ArchitectureSan Jose, CaliforniaBacked by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. Key Responsibilities: Architect the high-speed optical PHY of our next-generation product: TX path, RX path, clocking, and mixed-signal control loops against a system-level link budget shared with the photonics and laser teams.
Senior Physical Design Engineer Microsoft CorpSenior Physical Design EngineerMountain View, CA$119,800–$234,700 / yearRequired Qualifications: Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Masters Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Lead Compliance Engineer Heron PowerLead Compliance EngineerScotts Valley, California$150,000–$198,000 / yearWorking experience of UL1741, UL 347a , IEC 62109-1, IEC 62109-2, IEC 62040, IEC 62477, UL 9540, UL 1998, UL 840, UL 2891, UL5500, IEEE 1547, IEEE 2800. Then, in collaboration with the design engineering team, will demonstrate Heron's products meet or exceed all requirements, achieve all certifications, and successfully enter target markets.
Senior Physical Design Engineer/Lead Altera SemiconductorSenior Physical Design Engineer/LeadSan Jose, CaliforniaBachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline with 10+ years of industry experience in physical design, physical implementation, or SoC backend design, including the following: 10+ years of hands-on experience in digital ASIC and/or SoC physical design, including synthesis, floorplanning, place-and-route, clock tree synthesis (CTS), routing, engineering change order (ECO) implementation, and signoff. You will interface with architecture, logic design, DFT, CAD/EDA, and manufacturing teams to achieve our performance/power/area (PPA) goals, with particular emphasis on programmable logic structures, block and full-chip integration, and the unique demands of FPGA technologies (e.g., configurable logic blocks, routing fabrics, I/O rings, on-chip power domains).
Mixed-Signal Behavioral Modeling Engineer Apple IncMixed-Signal Behavioral Modeling EngineerCupertino, CAExcellent knowledge of digital logic gates, clocking and state elements Excellent knowledge of Verilog/SystemVerilog with ability to write behavioral code Ability to read custom circuit schematics and understand functionality Solid understanding of logic and behavioral simulations Basics of passive and active circuit elements, voltage and current sources, and analog blocks like amplifiers ADCs/DACs/Comparators Basics of SPICE circuit simulations Basics of timing synchronous digital logic Familiarity of writing scripts in PERL/Python and basic algorithms is a strong plus Familiarity with blocks such as PLLs/DLLs/SERDES is a strong plus Basics of digital signal processing and numerical analysis is a plus Basics of probability and statistical basics is a plus. If you are early in your journey towards a chip design career and wish to challenge yourself in a technical and multi-disciplinary effort, come join the Apple mixed-signal silicon design team.
Analog Mixed-Signal Modeling Software Engineer Apple IncAnalog Mixed-Signal Modeling Software EngineerCupertino, CAArchitect and maintain tools, frameworks, and simulation environments within the platform to support analog design workflows Design and implement software components for the platforms simulation engine, integrating multiple simulators to support analog/mixed-signal IP development Design and manage data storage architecture for the platform, including schemas, data models, and access layers that support analog/mixed-signal design data at scale Develop web-based interfaces and visualization tools within the platform to improve designer productivity and workflow transparency Partner with analog/mixed-signal design teams to gather requirements, triage issues, and prioritize platform feature development Drive platform deployment and rollout across design teams, and lead adoption efforts through onboarding, documentation, and trainingBS and 10 +years of relevant industry experienceExpert-level proficiency in Python and/or C++ Strong background in object-oriented programming (OOP) and software architecture design Experience with data storage systems, schema design, and database architecture Knowledge of event-driven programming and system-level simulation frameworks Experience developing web applications (e.g., Flask, React) and designing frontend user interfaces Experience with CI/CD pipelines, packaging, and deployment (e.g docker/cloud) Strong communication and cross-functional collaboration skills, with experience partnering with design engineers to gather requirements and drive adoption. Youll combine software engineering expertise with hardware knowledge to build automation frameworks, optimization algorithms, and modeling environments that help circuit designers create the physical interfaces connecting Apples processors to the real world.
Analog Simulation/Env Automation CAD Engineer Apple IncAnalog Simulation/Env Automation CAD EngineerSunnyvale, CAIn this role, you will have the opportunity to directly influence the circuit design on various technology nodes and develop CAD flows for analog circuit SPICE simulation, netlist, design environment, and analyze waveforms, results data processing. In this highly visible role, your primary responsibilities will include: Solving issues related to transistor level simulations on Analog, RF and Microwave applications with Spice simulators on command-line and Virtuoso environment.
Senior Substrate Layout Design engineer Zp Group LlcSenior Substrate Layout Design engineerSan Jose, CA$215,000–$270,000 / yearKeywords: Substrate layout, substrate, package substrate design, multi-die packaging, chiplet integration, CoWoS, MCM, BGA, FPGA, CPU, GPU, High-density interconnect, escape routing, signal integrity, power integrity, organic substrate, substrate tape-out, substrate DRC, cadence allegro APD, autocad, cadence SiP layout, EDA tools, Layout verification tools, ASIC, OSAT, mechanical co-design, floorplanning, design reviews. Piper Companies is seeking a Senior Substrate Layout Designer who will be responsible for leading the design of advanced multi-die substrate packages.
Senior Hardware Design Engineer Zp Group LlcSenior Hardware Design EngineerSan Jose, CA$210,000–$260,000 / yearThe Hardware Systems Architect role is ideal for a senior electrical engineering leader with deep expertise in high-speed, high-power board design who can guide complex hardware platforms used to bring up and validate next-generation custom ASICs. Piper Companies is seeking a Hardware Systems Architect around San Jose, CA to join a cutting-edge organization developing advanced networking hardware purpose-built for AI data centers.
Senior Physical Design Engineer E-SpaceSenior Physical Design EngineerSaratoga, CA$120,000–$220,000 / yearWe’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life. We are redefining how satellites are designed, manufactured and used—so we’re looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in-orbit activities.
FPGA Design Engineer - Avionics E-SpaceFPGA Design Engineer - AvionicsSaratoga, CAOur team members have a strong sense of dedication and responsibility; this includes a strong commitment to our mission to create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.
Principal Modeling Engineer Intuitive Surgical IncPrincipal Modeling EngineerSunnyvale, CAU.S. Export Controls Disclaimer: In accordance with the U.S. Export Administration Regulations (15 CFR §743.13(b)), some roles at Intuitive Surgical may be subject to U.S. export controls for prospective employees who are nationals from countries currently on embargo or sanctions status. Certain information you provide as part of the application will be used for purposes of determining whether Intuitive Surgical will need to (i) obtain an export license from the U.S. Government on your behalf (note: the government's licensing process can take 3 to 6+ months) or (ii) implement a Technology Control Plan ("TCP") (note: typically adds 2 weeks to the hiring process).
Senior BMS Electrical Engineer ArcherSenior BMS Electrical EngineerSan Jose, CA$144,000–$185,000 / yearArcher is an aerospace company based in San Jose, California building an all-electric vertical takeoff and landing aircraft with a mission to advance the benefits of sustainable air mobility. Our sights are set high and our problems are hard, and we believe that diversity in the workplace is what makes us smarter, drives better insights, and will ultimately lift us all to success.
Senior Analog And Mixed Signal Engineer NvidiaSenior Analog And Mixed Signal EngineerSanta Clara, CAWhat you'll be doing: You will work as part of a team to design and implement high speed interfaces and complex mixed-signal circuits using state-of-the-art sub-micron CMOS technologies and various EDA tools: High speed analog and hybrid Phase Locked loops and associated subblocks including VCO, charge-pump, dividers, state machines, LDO, bandgap, TDC, interpolator circuits, high speed buffers etc. Your other responsibilities will include architecture studies, circuit designs & simulations, floor-planning, instructing mask designers, reliability verifications and silicon bring-up.
Photonic Engineer, Platforms Infrastructure Google LLCPhotonic Engineer, Platforms InfrastructureSunnyvale, CAGoogle is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.
Hardware Performance Test Engineer, Engineering Labs, Platforms Google LLCHardware Performance Test Engineer, Engineering Labs, PlatformsSunnyvale, CAAs a Hardware Test Engineer, you will be supporting a team of hardware design, test, and qualification engineers who are responsible for prototype bring-up, validation, qualification, and failure analysis of machine learning technologies such as CPU/TPU/GPU, DDR memory, storages and high-speed interconnects. Preferred qualifications: Experience in more than one discipline related to hardware test, hardware qualification, and manufacturing (e.g., signal integrity, power circuit testing, optical testing, network testing, scripting, and hardware test execution automation using Python).
Product Engineer, Machine Learning Accelerators, Google Cloud Google LLCProduct Engineer, Machine Learning Accelerators, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
PCB Layout Engineer Meta Platforms IncPCB Layout EngineerSunnyvale, CAYou will collaborate closely with electrical engineers, mechanical engineers, and manufacturing partners to translate schematic designs into manufacturable, high-performance PCB layouts that meet the demanding constraints of consumer wearable products. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today-beyond the constraints of screens, the limits of distance, and even the rules of physics.
Silicon Validation Engineer, Google Cloud Google LLCSilicon Validation Engineer, Google CloudSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Debug and help root-cause failures, providing feedback to improve features like power management quality, performance, and reliability through generations of designs, including in pre-silicon prototyping platforms as well as through post-silicon bringup and production.
Senior Power Integrity Engineer, Platforms Infrastructure Google LLCSenior Power Integrity Engineer, Platforms InfrastructureSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Working with a collaborative and high impact team, you will design, analyze, validate, and deliver robust and innovative power delivery network solutions at the chip, package, board, rack, and pod levels.
NewSenior Hardware Development Engineer, NPD Hardware AmazonSenior Hardware Development Engineer, NPD HardwareCupertino, CALearn more about our benefits at CA, Cupertino - 183,000.00 - 247,600.00 USD annuallyUSA, WA, Bellevue - 159,200.00 - 215,300.00 USD annuallyUSA, WA, Seattle - 159,200.00 - 215,300.00 USD annuallyUSA, WA, Virtual Location - Washington - 159,200.00 - 215,300.00 USD annuallyCompanyAmazon Web Services, Inc. The ideal candidate is a strong hardware board designer with Ethernet networking experience in the areas of terabit switch fabrics, 10/40/100 gigabit interfaces, embedded CPU subsystems, and network processors.
Test Board Development Engineer, Silicon, Testchip Google LLCTest Board Development Engineer, Silicon, TestchipSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. You will work with silicon and product teams to ensure that goals are met with systems, and you will work with Application-Specific Integrated Circuit/Field-Programmable Gate Array (ASIC/FPGA), firmware, Signal Integrity/Power Integrity (SI/PI), and silicon development teams to ensure proper verification of test chip features.
Staff Verification Engineer Fortinet IncStaff Verification EngineerSunnyvale, CA$179,000–$219,000 / yearIn-depth knowledge of at least 2 of the following areas, with strong proficiency in each: Protocols & Networking: BGP, OSPF, LACP, STP/RSTP/MSTP, ARP, DNS, IPsec, IPv6, TLS, multicast, VXLAN, GRE, SD-WAN, QoS (Quality of Service). In this role, you will design, develop, and own the verification frameworks, test environments, and automation infrastructure for ASIC (Applied Specific Integrated Circuit) drivers and software features across our current and next-generation products.
Staff, Software Engineer Walmart IncStaff, Software EngineerSunnyvale, CA$143,000–$286,000 / yearImpact Youll Make You will build backend platforms that power real-time decisioning, large-scale data processing, and mission-critical retail workflows impacting millions of customers and associates globally. ### Role Overview As a Staff Engineer, you will act as a hands-on technical leader and system architect responsible for designing and delivering large-scale backend platforms and data processing systems.
Radio Frequency Hardware Engineer, Google Pixel Google LLCRadio Frequency Hardware Engineer, Google PixelMountain View, CAhomehomeHomeHomework_outlinework_outlineJobsJobsnoogler_hatnoogler_hatStudentsStudentsgooglegoogleHow we workHow we workhandymanhandymanHow we hireHow we hireperson_outlineperson_outlineYour careerYour careerhelp_outlineHelp linkfeedbackSend feedbackmore_vert HelpSend FeedbackSign inCareersCareershomeHomework_outlineJobsexpand_morenoogler_hatStudentsexpand_moregoogleHow we workexpand_morehandymanHow we hireexpand_moreperson_outlineYour careerexpand_morejob detailsarrow_backBack to jobs searchJobs search results3902 jobs matched. Radio Frequency Hardware Engineer Google Pixelshare linkCopy linkemailEmail a friendcorporate_fareGoogleplaceMountain View CA USAbar_chartMidMidExperience driving progress solving problems and mentoring more junior team members deeper expertise and applied knowledge within relevant area.