UNKNOWN

FEED

The role has two halves: you build working systems, reference architectures, and internal assets that advance org-level initiatives, and you build Live demos that let sales teams, customers, and partners use production-quality Amazon Connect AI agents. We work at the leading edge of the product, translating brand-new AI agent capabilities into reference architectures, sample code, and interactive experiences that the broader SA community, global sales teams, and partners rely on every day.

At Amazon, we don’t wait for the next big idea to present itself. We envision the shape of impossible things and then we boldly make them reality. So far, this mindset has helped us achieve some incredible things. Let’s build new systems, challenge the status quo, and design the world we want to live in. We believe the work you do here will be the best work of your life. 
Wherever you are in your career exploration, Amazon likely has an opportunity for you. Our research scientists and engineers shape the future of natural language understanding with Alexa. Fulfillment center associates around the globe send customer orders from our warehouses to doorsteps. Product managers set feature requirements, strategy, and marketing messages for brand new customer experiences. And as we grow, we’ll add jobs that haven’t been invented yet. 
It’s Always Day 1 
At Amazon, it’s always “Day 1.” Now, what does this mean and why does it matter? It means that our approach remains the same as it was on Amazon’s very first day – to make smart, fast decisions, stay nimble, invent, and stay focused on delighting our customers. In our 2016 shareholder letter, Amazon CEO Jeff Bezos shared his thoughts on how to keep up a Day 1 company mindset. “Staying in Day 1 requires you to experiment patiently, accept failures, plant seeds, protect saplings, and double down when you see customer delight,” he wrote. “A customer-obsessed culture best creates the conditions where all of that can happen.” You can read the full letter <a href="https://hiring.amazon.com/why-amazon/culture#/">here</a> 
Our Leadership Principles 
Our Leadership Principles help us keep a Day 1 mentality. They aren’t just a pretty inspirational wall hanging. Amazonians use them, every day, whether they’re discussing ideas for new projects, deciding on the best solution for a customer’s problem, or interviewing candidates. To read through our Leadership Principles from Customer Obsession to Bias for Action, visit <a href="https://www.amazon.jobs/principles" target="_blank">https://www.amazon.jobs/principles</a>

Amazon.com Inc

Senior Applied AI Solutions Architect - Amazon Connect, Applied AI

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Scale-up and scale-out interconnect: PCIe hierarchy and switching, high-speed Ethernet and SerDes, die-to-die and board-level links, copper versus optical at each tier, retimers, connectors and cable plant, topology, oversubscription, and the bandwidth and latency budget for each hop. Expert command of state-of-the-art copper and optical interconnect: PCIe, high-speed Ethernet and SerDes, DAC and twinax, backplane and cabled channels, AOCs, and pluggable or co-packaged optics, with the signal-integrity judgment to know where each approach stops working.

Mythic

Rack-Scale AI Hardware Architect

The ideal candidate has an engaging people style while being an OCI strategist, architect, and field advisor, enabling partners to deliver high-impact solutions centered on Oracle Cloud Infrastructure (OCI), hybrid and associated hyperscalers supporting Arrow's OCI go-to-market priorities. This role operates at the intersection of hyperscaler innovation with focus on Oracle Cloud Infrastructure (OCI), partner enablement, and customer transformation, driving scalable, repeatable cloud, data, AI, and security solutions through indirect sales motions.

YEAR

Arrow Electronics Inc

Senior Cloud Solution Architect (OCI)

Support post-silicon bring-up of the Networking functionalityBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of relevant industry experience architecting Networking datapaths and packet-processing pipelines and their hardware/software interfaces for NIC/DPU or comparable ASICs Experience with SmartNIC/IPU/DPU architectures and their usages: Network virtualization, storage disaggregation, overlay networking, virtual switch, firewall/ACLs, and PSP gateways, including offload mechanisms Experience with datacenter Networking technologies and protocols such as Ethernet, IPv6, TCP/UDP, Geneve, PSP, and SRv6, including offload mechanisms for TCP segmentation, reassembly, checksum, and receive-side scaling Experience with RDMA and storage protocols and fabrics, including RoCEv2 and NVMe/NVMe-over-Fabric (TCP and RDMA) Experience with congestion control (e.g., DCQCN) and emerging transports such as UET and comparable next-generation RDMA transports Experience with on-chip scheduling and arbitration architectures and quality-of-service mechanisms -- transaction/packet schedulers, arbiters, traffic shapers, and rate limiters (meters/policers, token buckets) -- and their impact on latency, fairness, bandwidth partitioning, and throughput Experience with datacenter network topologies and fabric architectures (e.g., Clos/fat-tree, rail-optimized fabrics) and their performance implications, including oversubscription, ECMP/load balancing, and end-to-end latency and congestion behavior Experience with symmetric and asymmetric cryptography concepts and inline data encryption (e.g., IPSec, PSP) Experience with domain-specific dataplane languages such as P4 Experience with data center workloads and their networking characteristics Experience with analytical performance-modeling methods (e.g., queueing theory, Little's Law, bandwidth-delay/outstanding-transaction sizing) Experience driving analysis independently and influencing architectural direction through data PhD in Computer Science, Computer Engineering or Electrical Engineering 15+ years of relevant industry experience architecting networking datapaths and packet-processing pipelines and their hardware/software interfaces for NIC/DPU or comparable ASICs Experience designing high-performance offload architectures for NVMe-over-Fabric Experience designing data-plane offload/acceleration architectures using programmable processors/engines (programmable parsers, match-action, etc.) Experience designing high-performance inline data encryption engines, such as for IPSec and PSP Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows Experience with GPU, machine learning, multi-threaded programming paradigm Experience with emerging RDMA transports such as UET and comparable next-generation RDMA protocols Experience with post-silicon performance validation and model-to-hardware correlation methodologies Experience with performance modeling and workload characterization for networking architectures, including analytical methods (e.g., queueing theory, Little's Law) and frameworks such as SystemC Experience with high-level synthesis, power-performance-area trade-off analysis, or PPA-driven microarchitectural optimization Experience designing scheduling, arbitration, or rate-limiting/traffic-management hardware (e.g., hierarchical schedulers, WRR/DWRR/strict-priority arbiters, shapers/policers) Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysisMeta builds technologies that help people connect, find communities, and grow businesses. Architect the Networking datapath for our DPUs - packet processing and offloads, Network virtualization and overlays, RDMA and storage transports, and inline security - from early path-finding through silicon bring-up Decide what runs in the datapath engines, what runs in firmware, and what stays in host software, and design the interfaces between them Define how software programs and controls the datapath - match-action tables, rule and flow programming, register and descriptor interfaces, and the offload interfaces firmware and drivers build on Work closely with firmware, driver, and software teams so the datapath and its interfaces are clean, efficient, and genuinely usable, and evolve them as needs change Work closely with design, DV, and PD teams on feature definition and PPA tradeoff; refine architecture to meet the design and PD constraints.

Meta Platforms Inc

DPU Networking Architect, Infrastructure Silicon

Analyze performance of current and future SmartNIC/IPU/DPU architectures with focus on end-to-end transaction flows, host-to-DPU offloading options, evaluation of SoC architectural options Quantify architectural/micro-architectural trade-offs wrt PPA to inform and guide design decisions Analyze and characterize DPU workloads to abstract key performance-relevant behaviors and incorporate into representative models and synthetic benchmarks Develop and enhance performance models, simulation tools, and methodologies to evaluate future DPU architectures Drive RTL performance validation, including development of comprehensive performance test plans, coverage criteria, and correlation of RTL results against architectural models Correlate pre-silicon performance projections with post-silicon measurements and drive methodology improvements based on findingsBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of relevant industry experience in developing analytical/tool based models and performance analysis with focus on networking and storage architectures Detailed understanding of DPU architectures: network virtualization, storage disaggregation, networking and storage protocols such as RoCE, NVMe, fabric architectures Experience in workload analysis and characterization, and abstracting key performance features into models for analysis Proficiency in languages for model development (e.g. Python, C/C++, SystemC) Experience with data center workloads and benchmarking methodologies Experience with RTL performance validation, including authoring and executing performance test plans and correlating pre-silicon performance models with post-silicon measurements Experience driving analysis independently and influencing architectural direction through data PhD in Computer Science, Computer Engineering or Electrical Engineering 15+ years of relevant industry experience in developing analytical/tool based models and performance analysis with focus on networking and storage architectures Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs Experience with post-silicon performance validation and model-to-hardware correlation methodologies Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysis Experience with GPU, machine learning, multi-threaded programming paradigm Experience with high-level synthesis, power-performance-area trade-off analysis, or PPA-driven microarchitectural optimizationMeta builds technologies that help people connect, find communities, and grow businesses.

DPU Performance Architect, Infrastructure Silicon

Support post-silicon bring-up of the I/O subsystemBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of relevant industry experience architecting I/O and system subsystems and their hardware/software interfaces - register and programming models, DMA and descriptor interfaces, doorbells, and offload interfaces - for NIC/DPU or comparable ASICs Experience with PCIe data link and transport protocols, including TLP formats, transaction types (posted/non-posted/completions), and ordering rules Experience with I/O virtualization technologies such as SR-IOV and SIOV Experience with PCIe capabilities such as Advanced Error Reporting, Downstream Port Containment, and Integrity and Data Encryption Experience with on-chip scheduling and arbitration architectures and quality-of-service mechanisms - transaction/packet schedulers, arbiters, traffic shapers, and rate limiters (meters/policers, token buckets) - and their impact on latency, fairness, bandwidth partitioning, and throughput Experience with symmetric and asymmetric cryptography concepts and inline data encryption (e.g., AES-XTS, AES-GCM) Experience with x86 and/or ARM system architecture, including virtualization technologies, IOMMUs, and interrupt virtualization Experience with data center workloads and their I/O characteristics Experience driving architectural decisions independently and influencing their direction through data PhD in Computer Science, Computer Engineering or Electrical Engineering 15+ years of relevant industry experience architecting I/O and system subsystems and hardware/software interfaces for NIC/DPU or comparable ASICs Experience designing PCIe endpoints and root complexes Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysis Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs Experience with system-management concepts including server/BMC interactions, and protocols such as I2C, I3C, USB/Ethernet, USB/MCTP, and SPI/eSPI Experience designing high-performance DMA engines and offload accelerators, such as for cryptography and compression Experience with post-silicon performance validation and model-to-hardware correlation methodologies Understanding of Confidential Computing use cases and the related PCIe protocols -- Data Object Exchange (DOE), Security Protocol and Data Model (SPDM), Management Component Transport Protocol (MCTP), and TEE Device Interface Security Protocol (TDISP)Meta builds technologies that help people connect, find communities, and grow businesses. Own the I/O subsystem architecture for our DPUs - PCIe, DMA and offload engines, I/O virtualization, confidential computing, and system management -- from early path-finding through silicon bring-up Decide what runs in hardware, what runs in firmware, and what stays in host software, and design the interfaces between them Define the hardware/software interface - register and programming models, descriptor and doorbell interfaces, error and interrupt models, and the offload interfaces firmware and drivers build on Work closely with firmware, driver, and software teams so the interface is clean, efficient, and genuinely usable, and evolve it as their needs change Weigh the performance, power, and area trade-offs behind your choices and back them with data, partnering with performance modeling where deeper analysis is needed Work closely with design, DV, and PD teams on feature definition and PPA tradeoff; refine architecture to meet the design and PD constraints.

DPU IO Architect, Infrastructure Silicon

Perform detailed calculations to specify computation throughput, memory bandwidth and latency; evaluate performance v/s area v/s power tradeoffs Drive the architecture definition of one or more of the following ASIC sub-systems: compute, memory, Network-On-Chip (NoC), collectives, debug etc. and chiplet based multi-die SoCs Identify appropriate workloads and micro-benchmarks to be used for performance analysis and drive this analysis on simulation and emulation platforms to define and validate the architecture Evangelize your innovative architectural solutions with your peers and leadership, while mentoring members of the architecture team Collaborate with cross functional teams working on RTL design, Design Verification, Firmware/Software development, Pre-Post silicon validation and Program Management to deliver first pass functional silicon on an aggressive schedule Collaborate with software and firmware teams to ensure that the ASIC meets end to end application performance goals while maintaining ease and efficiency of software developmentBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience Experience and knowledge of Computer Architecture concepts such as microprocessor architecture, memory systems, on-chip interconnection networks, hardware/software partitioning etc 12+ years of prior experience in defining and delivering multiple high performance ASICs into production, with focus on architecture definition and performance analysis Experience in ASIC performance modeling, microarchitectural analysis, or pre-silicon simulation for custom silicon or SoC designs Proficiency in C++ and Python for developing simulation models, automation frameworks, and performance analysis tools Experience with performance analysis of data center, AI accelerator, or high-performance computing workloads on custom silicon Experience defining architecture and microarchitectural specifications and driving cross-functional alignment across architecture, RTL, and physical design teams Familiarity with post-silicon performance validation and model-to-hardware correlation methodologies Programming in C or C++ with knowledge of mapping hardware algorithms to efficient C/C++ code Master's or PhD degree in Electrical Engineering, Computer Engineering or related field Domain knowledge in one or more of power/performance tradeoffs, ML networks, ML frameworks such as Pytorch Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designsMeta builds technologies that help people connect, find communities, and grow businesses. In this role, you will own ASIC architecture specification, establish the performance modeling methodology and long-term silicon roadmap strategy, partnering with other silicon, and software teams to ensure Meta's infrastructure silicon meets the demanding throughput, latency, and efficiency targets required at hyperscale.

Machine Learning SoC Architect

The successful candidate will work directly with clients, assessing their needs, designing tailored solutions, and supporting business initiatives in alignment with defined roadmaps. This role is technology agnostic but emphasizes solutions leveraging heavily on AWS and/or GCP environments, incorporating elements of open-source, PaaS, and SaaS components.

CoverGo

Solutions Architect (Insurance) - Fully Remote

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ADAPTED_NOW

Lead architectural design for the highest-complexity GTM systems — multi-system integrations, enterprise-scale agentic workflows, real-time event processing, and cross-platform data orchestration across Salesforce, NetSuite, Marketo, and custom data stores. As Lead AI Architect, GTM Systems, you will set the technical vision for how Samsaras GTM technology organization builds AI-powered automation: from low-code platforms that put power in the hands of operators, to custom agentic pipelines that tackle the most complex GTM workflows.

Samsara

AI Architect - GTM Systems

Ivy Exec

Other Responsibilities: Collaborate with cross-functional teams (Architecture, RTL Design, Verification, DFT, Physical Design, Firmware/Software, Systems, Quality, and Product/Customer teams) to align security, safety, test, and product requirements and to support customer discussions, audits, and security reviews. Job Responsibilities: Define SoC hardware security architecture and requirements, including HSM specification, secure boot/RoT concepts, and cryptographic IP integration strategies.(AES/SHA/PKA/PUF/PQC etc).

NXP Semiconductor, Inc.

Hardware Security Architect

This role partners with business and technology leaders to deliver sustainable solutions, drives platform governance and innovation, mitigates risk, and mentors technical teams while guiding the organization''s ServiceNow roadmap and architectural direction. Supervisory Responsibilities: Provides technical leadership and architectural direction to administrators, developers, integration specialists, partners, and matrixed contributors; direct people management is not required.

BDO International Ltd

ServiceNow Platform Architect

With a proven track record in architecting and delivering cutting-edge solutions for complex system-level challenges, you possess deep expertise in semiconductor, EDA, or high-tech environments. You are adept at translating customer requirements into robust, scalable architectures that anticipate future needs, and you excel at navigating ambiguity to deliver strategic clarity.

NXP Semiconductors NV

Software Architect

You'll work closely with engineering, product, UX, and platform architects to shape the next generation of Procore's mobile and cross-platform strategy, including cross-platform shared logic (e.g., Kotlin Multiplatform), a federated GraphQL backend-for-frontend layer, and the broader set of Mobile Platform capabilities such as offline sync, CI/CD, observability, and security posture etc. that keep mobile quality and velocity high as the platform scales. A criminal history may have a direct, adverse, and negative relationship on the following job duties, potentially resulting in the withdrawal of the conditional offer of employment: 1. appropriately managing, accessing, and handling confidential information including proprietary and trade secret information, as well as accessing Procore's information technology systems and platforms; 2. interacting with and occasionally having unsupervised contact with internal/external customers, stakeholders, and/or colleagues; and 3. exercising sound judgment.

Procore Technologies

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BDO USA PC

You will work alongside designers, builders, estimators, purchasers, project managers, field teams, and outside consultants to develop homes that are beautiful, practical, buildable, and responsive to each client and site. Moontower Design + Build is looking for an experienced Residential Architect / Lead Designer who can combine strong design judgment with the technical knowledge, organization, and leadership required to deliver thoughtful custom homes.

Moontower

Residential Architect / Lead Designer

The Hire Talent

OTHER

Support architecture and solution discussions involving SAP, WMS/WES/WCS, AMRs, robotics, controls/PLCs, IoT, APIs, and industrial automation platforms . This role will work across business teams, IT/GIS, engineering, and external technology partners to take initiatives from early requirements and solution definition through implementation and production readiness.

Black Rock Groups

SAP Solution Architect - WMS and Industrial Automation

Ceipal

Serving as both design authority and hands-on technical lead, the PSA Architect will translate complex finance and operational requirements into scalable solutions spanning project and contract setup, time and expense capture, resource and utilization management, customer accounts, billing, invoicing, revenue recognition, accounts receivable, and collections. Deep functional knowledge of Workday Projects, Project Billing, Customer Contracts, Customer Accounts, Revenue Management, Time Tracking, Expenses, Accounts Receivable, Collections, and related accounting processes.

Aon Plc

Workday PSA, Professional Services Automation Architect

The ideal candidate brings deep experience designing large-scale distributed systems, leading large modernization programs, and operationalizing AI capabilities in production with strong attention to reliability, performance, security, maintainability, cost, and compliance. We offer IT solutions and expert services that eliminate the daily hurdles preventing healthcare providers from focusing entirely on their patients - powered by our vision to create a thriving ecosystem that delivers accessible, high-quality, and sustainable healthcare for all.

athenahealth Inc

Software Architect, Scheduling

Architect multi-agent systems for AIOps, including anomaly detection, event correlation, ITSM ticket triage, and self-healing runbooks that reduce mean time to detect (MTTD) and mean time to resolve (MTTR). They will set the AI strategy for the Cloud business unit and turn it into working agents that reduce manual effort, improve reliability, and keep Cloud environments secure, compliant, and cost-effective.

Harris Computer Systems

Principal AI Cloud Architect - Azure Cloud

The ideal candidate will have extensive knowledge of CPU and SoC power management architecture for datacenter SoCs, including experience in microarchitecture and design of power management components for a modern SoC. Minimum Qualifications: Bachelor''s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

Architect Jobs in Austin, TX

Senior Applied AI Solutions Architect - Amazon Connect, Applied AI Amazon.com Inc

Rack-Scale AI Hardware Architect Mythic

Senior Cloud Solution Architect (OCI) Arrow Electronics Inc

DPU Networking Architect, Infrastructure Silicon Meta Platforms Inc

DPU Performance Architect, Infrastructure Silicon Meta Platforms Inc

DPU IO Architect, Infrastructure Silicon Meta Platforms Inc

Machine Learning SoC Architect Meta Platforms Inc

Solutions Architect (Insurance) - Fully Remote CoverGo

AI Architect - GTM Systems Samsara

Hardware Security Architect NXP Semiconductor, Inc.

ServiceNow Platform Architect BDO International Ltd

Software Architect NXP Semiconductors NV

Software Architect Procore Technologies

ServiceNow Platform Architect BDO USA PC

Residential Architect / Lead Designer Moontower

SAP Solution Architect - WMS and Industrial Automation Black Rock Groups

Workday PSA, Professional Services Automation Architect Aon Plc

Software Architect, Scheduling athenahealth Inc

Principal AI Cloud Architect - Azure Cloud Harris Computer Systems

Server Power Management Sr. Staff Architect Qualcomm Inc

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