Key ResponsibilitiesDefine the end-to-end verification strategy across block, subsystem, and full-chip levels aligned with tapeout milestonesAuthor and review verification plans mapping specifications to features, stimulus strategies(traditional stimulus generation, compiler driven), coverage goals, and sign-off criteriaArchitect scalable UVM-based testbench environments including agents, scoreboards, reference models, and coverage monitorsDrive constrained-random stimulus development targeting protocol interactions, concurrency, error injection, and corner casesDefine and close functional coverage models through systematic hole analysis, targeted tests, seed optimization, and regression tuningDeploy SystemVerilog Assertions for protocol compliance, interface checks, and design invariants across all simulation runsLead full-chip verification including boot sequences, interrupt handling, DMA flows, power-on reset, and multi-block interactionsEnsure CDC, RDC, and multi-power-domain verification in coordination with specialist tools and teamsDebug complex simulation failures spanning multi-block interactions, protocol violations, race conditions, and timing-dependent corner casesOwn the bug lifecycle - triage, prioritization, tracking, fix verification, and cross-functional resolution with RTL designers and architectsManage the regression framework - defining suites, maintaining stability, optimizing throughput, and integrating with CI/CD pipelinesCoordinate simulation-to-emulation handoff ensuring verification collateral transitions effectively to emulation environmentsCollaborate cross-functionally with Compiler Team, RTL design, DFT, physical design, and post-silicon validation teamsLead, mentor, and grow the verification engineering team while maintaining a high quality bar through rigorous reviewsRepresent verification readiness in tapeout sign-off reviews and program-level decisionsSupport running gate-level simulations as part of design signoff. This role demands a strong blend of technical depth in modern verification methodologies (UVM, embedded C and compiler generated trace driven testing) and the leadership ability to execute across a multi-block chip program on schedul.e The DV Lead will help shape our internal processes for building robust and verified designs, including the company's second product line, which will scale computing performance and capability, while improving energy efficiency.