Senior Design Verification Engineer - PCIe Subsystem (PCIe Gen6) ACL DigitalSenior Design Verification Engineer - PCIe Subsystem (PCIe Gen6)San Jose, CAVerify CPU subsystem functionality, interconnects, interrupts, coherency, power management, and exception handling. Develop verification plans, UVM testbenches, test cases, assertions (SVA), and functional coverage.
Senior Design Verification Engineer - Memory Controller Subsystem (HBM) ACL DigitalSenior Design Verification Engineer - Memory Controller Subsystem (HBM)San Jose, CADevelop verification plans, UVM testbenches, test cases, assertions (SVA), and functional coverage. Execute regressions, debug RTL/design issues, and drive functional and code coverage closure.
Principal Design Verification Engineer Bolt GraphicsPrincipal Design Verification EngineerSunnyvale, CaliforniaBolt is committed to building a diverse and inclusive environment in which we recognize and value each other’s differences as well as fostering a culture that promotes its core values: Professionalism, Integrity, and Respect. You will lead a team of verification engineers, define methodologies, drive coverage closure, and ensure high-quality silicon delivery.
Design Verification Engineer ACL DigitalDesign Verification EngineerCADevelop and maintain UVM-based verification environments Verify CPU subsystems and instruction execution Implement constrained-random testing Integrate Instruction Set Simulators ISS with DV environments Debug complex functional issues across hardware and testbench. 5 years Design Verification experience Strong skills in • SystemVerilog • UVM • Testbench architecture Experience verifying processor or CPU subsystems.
Design Engineer Aditi ConsultingDesign EngineerSunnyvale, CA$82–$85 / hourConsent to Communication and Use of AI Technology: By submitting your application for this position and providing your email address(es) and/or phone number(s), you consent to receive text (SMS), email, and/or voice communication whether automated (including auto telephone dialing systems or automatic text messaging systems), pre-recorded, AI-assisted, or individually initiated from Aditi Consulting, our agents, representatives, or affiliates at the phone number and/or email address you have provided. Perform power/performance measurement across design stages using PPA RTL, PtPx tool; correlate results with post silicon and feed back to design/power-modeling teams.
Senior Staff Software Engineer, GCBP Transact Google LLCSenior Staff Software Engineer, GCBP TransactSunnyvale, CATeams work all across the company, in areas such as information retrieval, artificial intelligence, natural language processing, distributed computing, large-scale system design, networking, security, data compression, user interface design; the list goes on and is growing every day. Quality Gates and Release Governance: Partner with engineering and business stakeholders to define and enforce enterprise grate automated gatekeeping strategies (including presubmit integrations and release certification) to reduce production support tickets and outages.
SoC Test Infrastructure Engineer, Post Silicon NPI Google LLCSoC Test Infrastructure Engineer, Post Silicon NPISunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) in preparation for high-volume manufacturing (HVM), working with ATE vendors and internal cross-functional teams.
Firmware Engineer VoltaiFirmware EngineerPalo Alto, CaliforniaWe are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents. Backed by Silicon Valley’s top investors, Stanford University, and CEOs/Presidents of Google, AMD, Broadcom, Marvell, etc.
Senior RF Test & PCB Design Engineer ProdaptSenior RF Test & PCB Design EngineerSan Jose, CaliforniaRF Characterization: Utilize lab equipment (VNAs, Spectrum Analyzers, Signal Generators) to perform various RF measurements and verify simulation-to-measurement correlations. Cross-functional Collaboration: Work closely with RFIC Design and System Engineering teams to define board requirements and provide feedback on chip-level performance.
Senior Quality Assurance Engineer DanaherSenior Quality Assurance EngineerNewark, CA$116,000–$159,500 / yearAddress nonconformities and deviations by performing risk assessments, identifying root causes, conducting failure mode analysis, defining disposition, and supporting effective corrective and preventive actions to prevent recurrence. Serve as the primary Quality Engineering representative on cross-functional teams for new product introduction and manufacturing sustainment, providing strategic input on design control, risk management, and quality compliance.
Principal Hardware Engineer - Fluidics - Pleasanton, CA Calyxo IncPrincipal Hardware Engineer - Fluidics - Pleasanton, CAPleasanton, CA$250,000–$270,000 / yearIndividually contribute to mechanical/electromechanical design for critical fluidics subsystem components and assemblies and provide expert design review of other team-members designs. This role focuses on the design and control of irrigation and aspiration systems, combining pumps, valves, sensors, tubing sets, and embedded software into safe and reliable products.
Staff Functional Safety Engineer Rivian Automotive IncStaff Functional Safety EngineerPalo Alto, CA$171,100–$213,900 / yearRivian may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law. Rivian may share your Candidate Personal Data with (i) internal personnel who have a need to know such information in order to perform their duties, including individuals on our People Team, Finance, Legal, and the team(s) with the position(s) for which you are applying; (ii) Rivian affiliates; and (iii) Rivian's service providers, including providers of background checks, staffing services, and cloud services.
Senior Mixed Signal Design Engineer NvidiaSenior Mixed Signal Design EngineerSanta Clara, CAThis position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What we need to see: Master and/or PhD of Science in Electrical Engineering, Computer Engineering or related field with strong analog design background (or equivalent experience).
Senior Reliability Engineer ALSOSenior Reliability EngineerPalo Alto, CaliforniaWe’re a passionate team of builders, dreamers, doers and innovators, focused on creating entirely new (not to mention, innovative and delightful) vertically integrated, small EVs designed to meet the global mobility challenges of today and tomorrow. Establish reliability targets and metrics for new product development, covering actuators, batteries, drive units, PCBAs, chassis, and various low-voltage electronic systems.
Design Verification Engineer Broadcom CorporationDesign Verification EngineerSan Jose, CABroadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and embedded IP, is looking for an experienced verification engineer that will be responsible for modeling and verification activities related to complex digital and mixed signal (MXS) IP blocks used in Broadcom's ASIC developments. Education and Experience required: BS in Electrical Engineering / Computer Engineering and 12+ years of related experience; or an MS in Electrical Engineering / Computer Engineering and 10+ years of related experience.
Senior Principal Electrical Engineer Coherent CorpSenior Principal Electrical EngineerSanta Clara, CAKnowledge of fiber optics test and measurement equipment including BERTs, sampling/real-time oscilloscopes, VNAs, spectrum analyzers, optical spectrum analyzers, optical power meters, wavelength meters, tunable lasers, attenuators, thermal control systems, and automated handlers. Expertise selecting PCB materials and stackups for high-frequency applications, including Rogers, Panasonic and equivalent low-loss laminate families, hybrid stackups, prepreg/core choices, resin systems, glass weave effects, fabrication tolerances, and cost/performance tradeoffs.
Sr. Staff EMC Engineer Rivian Automotive IncSr. Staff EMC EngineerPalo Alto, CA$213,000–$266,000 / yearRivian may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law. Rivian may share your Candidate Personal Data with (i) internal personnel who have a need to know such information in order to perform their duties, including individuals on our People Team, Finance, Legal, and the team(s) with the position(s) for which you are applying; (ii) Rivian affiliates; and (iii) Rivian's service providers, including providers of background checks, staffing services, and cloud services.
NewSr. DSP Systems Engineer Silicon Engineering Space Exploration Technologies CorpSr. DSP Systems Engineer Silicon EngineeringPalo Alto, CA$175,000–$280,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). ITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
Senior Civil (Traffic) Engineer City of Dublin CASenior Civil (Traffic) EngineerDublin, CA$148,831.90–$186,033.12 / yearIdeal Candidate: The ideal candidate for the Senior Civil (Traffic) Engineer position is a knowledgeable, proactive, and solution-oriented transportation professional who thrives in a dynamic municipal environment and demonstrates strong technical expertise in transportation planning, traffic engineering, traffic operations, and project delivery. Particular emphasis may be in the areas of general engineering, transportation planning, traffic engineering, subdivision and private development plan checking, assessment district engineering, permit issuance, capital project planning, design and construction management, and public works inspection services.
Forward Deployed Engineer (Fde) Reasonable AIForward Deployed Engineer (Fde)San Francisco, CAWorld-class team and environment: an opportunity to build alongside deeply experienced founders , in a well-funded company that’s backed by industry leading VCs and angels including Oriol Vinyals, Zoubin Ghahramani, Jonathan Frankle and Guy Podjarny, amongst many others. Time spent inside or close to a high-accountability engineering culture in the mould of a Stripe, Cloudflare, AWS, Datadog, MongoDB or similar; you understand the value of correctness and verification.
Test Engineer - R&D aureliussystems.comTest Engineer - R&DSan Francisco, CaliforniaThis role spans lab testing, environmental testing, and frequent field deployments, working directly with hardware, software, and systems engineers to ensure what we build actually works under real operating conditions. About Aurelius Systems Aurelius Systems is a directed energy company developing edge-deployed laser systems for counter-unmanned aerial systems (cUAS)—we shoot down drones with laser guns.
GNC Engineer, Advanced Modeling Xona Space Systems, Inc.GNC Engineer, Advanced ModelingBurlingame, CAWith Pulsar - the world's most advanced PNT satellite infrastructure in Low Earth Orbit - Xona will offer a future-proof, backwards-compatible global positioning system optimized for absolute precision, superior power, and robust protection. You will build nonlinear six-degree-of-freedom simulation environments, develop flexible-body and vehicle subsystem models, and validate those models using analytical, test, and flight data.
NewSr. FPGA Verification Engineer Reliable Robotics CorpSr. FPGA Verification EngineerMountain View, CAFPGA engineers at Reliable Robotics have a unique opportunity to work at the heart of a vertically integrated technology stack that goes all the way up to aircraft level, with a direct impact on the aircrafts capabilities and requirements. FPGA Verification Engineer, you will own the FPGA integration and test environment for multiple airborne products including their test benches & simulation, continuous integration, timing analysis, elemental analysis, and build.
Senior Mechanical Engineer Eichleay IncSenior Mechanical EngineerSan Francisco, CA$115,000–$145,000 / yearWhile performing duties of this job, you would occasionally be required to stand, walk, sit, reach with hands and arms, climb or balance, stoop or kneel, talk and hear (this includes being able to hear and talk on site based communication equipment), distinguish between various colors, be able to hear safety tones/notifications, and use fingers and hands to feel objects, tools, temperature or controls. Technical Competence: Advanced experience developing, reviewing, and approving technical documents and drawings to support the procurement, repair, or modification of fixed and rotating equipment, including pressure vessels, tanks, separators, filters, heat transfer equipment, pumps and compressors.
Principal Test Engineer (Optical Module) Marvell Technology IncPrincipal Test Engineer (Optical Module)Santa Clara, CAHighlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. The Optics team develops highly integrated silicon photonics platforms that combine optical components, analog front ends, controller ASICs, and DSPs, enabled by robust embedded firmware.
Senior Systems Engineer KLA CorpSenior Systems EngineerMilpitas, CA$105,900–$180,000 / yearEnabling the movement towards advanced chip design, KLA''s Global Products Group (GPG), which is responsible for creating all of KLA's metrology and inspection products, is looking for the best and the brightest research scientist, software engineers, application development engineers, and senior product technology process engineers. Each CoE contributes not just talent and deliverables per discipline toward product programs, but also subject matter expertise, best practices, roadmaps, specialized facilities, apparatus, models, and analytics.
Senior Formal Verification Engineer, GPU Kernels NVIDIA CorpSenior Formal Verification Engineer, GPU KernelsSanta Clara, CAThe scope of these efforts ranges from developing new algorithms to evaluating them, from building tools to automating workflows, from joining architecture discussion to learning the latest technologies from the research community. NVIDIA's Deep Learning Safety Team is hiring engineers to build the verification tools that prove these kernels behave correctly, enabling their deployment in a large range of environments, including safety-critical systems.
Senior Mechanical Engineer - Stress Analysis ZiplineSenior Mechanical Engineer - Stress AnalysisSouth San Francisco, CA$145,000–$220,000 / yearOn any given day you could be building test articles in our composites/prototype labs, developing simple models to inform design trade studies, performing structural tests to validate analysis, working across disciplines to tackle complex system level challenges, root causing a test or field failure, or in the field supporting flight tests. Measurable outcomes you will be accountable for: reduction in product level cost per delivery, GFEM release cadence (e.g., weekly/monthly to match config updates), reduction in structural repeat failures across fleet, mass or margin improvements from design trades, and model-to-test correlation metrics.
Silicon Validation Engineer 5 Lattice Semiconductor CorpSilicon Validation Engineer 5San Jose, CaliforniaYou will get significant exposure and training in the following areas: Chance to learn FPGA and it’s build block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, MIPI, Fabric, I/O etc but not limited. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry.
Embedded Software Engineer - Special Purpose Software Joby AviationEmbedded Software Engineer - Special Purpose SoftwareSanta Cruz, California$108,200–$193,600 / yearFull timeRequired: Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering, Mechatronics, Physics, Mathematics, Robotics, or a related technical field with 3+ years of relevant industry experience in embedded software development; or a Master’s degree in a related technical field with 1+ years of relevant experience; or equivalent demonstrated experience through a robust portfolio of designed and deployed embedded software systems. Company Overview: Imagine a piloted air taxi that takes off vertically, then quietly carries you and your fellow passengers over the congested city streets below, enabling you to spend more time with the people and places that matter most.
Senior Staff Electrical Engineer IonQ IncSenior Staff Electrical EngineerSan Francisco, CA$167,808–$219,704 / yearPlease note that in the absence of confirming you are a U.S. Person for export control and government contracts work purposes, IonQ may choose not to apply for a license or decline to use a license exception (if available) for you to access export-controlled technology that may require authorization, and similarly, you may not qualify for government contracts work that requires U.S. Persons, and IonQ may decline to proceed with your application on those bases alone. IonQ's newest generation of quantum computers, the IonQ Tempo, is the latest in a line of cutting-edge systems that have been helping customers and partners including Amazon Web Services, and AstraZeneca achieve 20x performance results and accelerate innovation in drug discovery, materials science, financial modeling, logistics, cybersecurity, and defense.
Senior RF Antenna Design Engineer ZiplineSenior RF Antenna Design EngineerSouth San Francisco, CA$160,000–$250,000 / yearOur customers include the world's largest and most prominent healthcare systems, governments, retailers, restaurants and global businesses who rely on us to save lives, reduce emissions, increase economic opportunity, and provide delivery from point A to point B as fast as possible. Work on antenna arrays, distributed antenna systems, single aperture antennas as well as co-located antenna integrations to deliver on radiated performance, and support cross functionally to deliver: coexistence, desense, regulatory and product level requirements.
Senior / Staff Electrical Engineer - Avionics ZiplineSenior / Staff Electrical Engineer - AvionicsSan Francisco, CA$160,000–$225,000 / yearOur customers include the world's largest and most prominent healthcare systems, governments, retailers, restaurants and global businesses who rely on us to save lives, reduce emissions, increase economic opportunity, and provide delivery from point A to point B as fast as possible. You will work closely with electrical, mechanical, firmware, software, manufacturing, test, quality, supply-chain, and operations teams to build hardware that is safe, robust, manufacturable, and ready for global operation.
Principal, Design Verification Engineer, UAL and PCIe Subsystems Veracity Software IncPrincipal, Design Verification Engineer, UAL and PCIe SubsystemsSanta Clara, CAFull Name: Degree (BS/MS/PhD) – Major, University & Completion Year: Total ASIC/SoC Design Verification Experience (Years): Experience with SystemVerilog (Years – details): Experience with UVM (Years – details): Experience writing Verification Test Plans (Yes/No – details): Experience building Constrained Random Verification Environments (Yes/No – details): Experience with Coverage-Driven Verification (Yes/No – details): Experience with Python and/or Perl Scripting (Years – details): Experience using EDA Verification Tools (Specify tools): Experience with Object-Oriented Programming (Yes/No – details): Linux Experience (Years – details): C++ Programming Experience (Years – details): ARM Assembly Experience (Yes/No – details): Experience with UAL Protocol (Yes/No – details): Experience with PCIe Protocol (Years – details): Experience verifying Multi-Core SoCs (Yes/No – details): Experience with Boot Code Verification (Yes/No – details): Motivation / Reason for interest in this position: Contact Number: Email ID: LinkedIn Profile URL: Full Address (Street, City, State, Zip Code): Notice Period: Current Work Authorization Status: Expected Salary: Are you able to relocate on your own expenses and work Santa Clara, CA – Onsite ?. This role involves creating sophisticated verification methodologies, writing comprehensive verification plans, developing constrained-random verification environments, debugging complex hardware issues, and collaborating closely with design engineers to ensure robust silicon validation.
Design Verification Engineer Broadcom IncDesign Verification EngineerSan Jose, CABroadcom's ASIC Products Division (APD), a worldwide leader in the design of complex custom ASICs and embedded IP, is looking for an experienced verification engineer that will be responsible for modeling and verification activities related to complex digital and mixed signal (MXS) IP blocks used in Broadcom's ASIC developments. Education and Experience required: BS in Electrical Engineering / Computer Engineering and 12+ years of related experience; or an MS in Electrical Engineering / Computer Engineering and 10+ years of related experience.
Custom SOC IP Verification Engineer NVIDIA CorpCustom SOC IP Verification EngineerSanta Clara, CAYou will play a key role in verifying the correctness, performance, and compliance of on-chip fabrics and interconnect subsystems - from IP bring-up through full chip integration - ensuring robust and high-performance connectivity across complex SoC designs. Design and implement constrained-random and directed SystemVerilog testbenches targeting interconnect fabrics, network-on-chip (NoC) topologies, and multi-agent SoC integrations.
NewGPU Verification Engineer - New College Grad 2026 NVIDIA CorpGPU Verification Engineer - New College Grad 2026Santa Clara, CAThis position offers the opportunity to have real impact in a progressive, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What You'll Be Doing: As a member of the GPU verification team, you will be responsible for verifying the ASIC design, architecture and micro-architecture of NVIDIA GPUs and SoCs using sophisticated verification methodologies.
Senior Formal Verification Engineer NvidiaSenior Formal Verification EngineerSanta Clara, CAYou will employ advanced formal techniques to obtain sufficiently bounded proofs while working with architects, designers, and pre- & post-silicon verification teams to accomplish your tasks. You will collaborate with a team of highly skilled engineers to develop and implement formal verification methodologies using formal verification tools, define the verification scope, and ensure design correctness.
Verification Engineer, Emulation And Prototyping NvidiaVerification Engineer, Emulation And PrototypingSanta Clara, CAUnderstanding of performance-sensitive validation methodologies for large-scale emulation environments, including efficient logging, synchronization, memory handling, and protocol traffic generation and experience enabling pre-silicon software validation, firmware bring-up, or system-level debug on emulation platforms is a plus! What we need to see: BS (or equivalent experience) in Electrical Engineering, Computer Engineering, or related fields with 5+ years of experience, or MS with 3+ years of proven experience in FPGA prototyping and/or hardware emulation.
Sr. ASIC Verification Engineer TensordyneSr. ASIC Verification EngineerSunnyvale, CaliforniaResponsibilities: Your responsibilities will be wide-ranging and and run the gamut of working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular SystemVerilog and UVM, handling bug tracking and coverage convergence and developing scripts and methodologies for the front-end ASIC flow. This ASIC’s design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to deliver the high-performance multi-chip silicon solutions that are at the heart of Tensordyne’s vertically integrated, generative AI inference acceleration systems for data centers.
Sr. Staff ASIC Verification Engineer TensordyneSr. Staff ASIC Verification EngineerSunnyvale, CaliforniaResponsibilities: Your responsibilities will be wide-ranging and and run the gamut of working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular SystemVerilog and UVM, handling bug tracking and coverage convergence and developing scripts and methodologies for the front-end ASIC flow. This ASIC’s design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to deliver the high-performance multi-chip silicon solutions that are at the heart of Tensordyne’s vertically integrated, generative AI inference acceleration systems for data centers.
ASIC Design Verification Engineer Palo Alto Networks IncASIC Design Verification EngineerSanta Clara, CA$106,400–$172,150 / yearYour Experience BS in EE, CE, or CS required or equivalent military experience required - MSEE preferred Minimum 3 years experience in ASIC design verification Demonstrated success in taking multiple ASIC products from concept to mass production Expertise in SystemVerilog and UVM Technical strength in the following areas is requiredDefining test plans, including comprehensive adversarial testing Developing rich functional coverage models Creating powerful and scalable test benches Implementing sophisticated self-checking infrastructure with reference models and scoreboards Developing reusable constrained-random tests Debugging failures Closing coverage Experience in the following areas is preferredNetworking and cyber security Formal property verification Silicon validation - bringup, test, debug, and regression Creating models in Python and C/C++ Writing driver code in C Skilled in writing powerful, modular, and scalable programs in Python, Perl, and UNIX shell to automate verification tasks, especially regression testing Demonstrated ownership and independence in planning, debugging complex failures, closing metrics-driven tasks, driving vendors, and reporting status Strong leadership, collaboration, and communication skills. Your Impact Collaborate with engineers in software, architecture, design, and verification teams to create comprehensive pre-silicon verification plans across simulation, emulation, and formal verification Plan and execute every aspect of simulation test plans using sophisticated coverage-driven, constrained-random methodologies Develop flows, methodologies, and infrastructure for emulation - Create, run, and debug emulation tests in close collaboration with system architects, software engineers, and ASIC designers Define new tools and methodologies to continuously improve quality and velocity Create powerful programs in Python to automate triage, coverage closure, and metrics-driven verification.
Senior Asic Verification Engineer NvidiaSenior Asic Verification EngineerSanta Clara, CAThe base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. This position offers the opportunity to have real impact in a dynamic and technology-focused company, with your work influencing product lines ranging from consumer graphics to artificial intelligence.
Formal Verification Engineer - New College Grad 2026 NVIDIA CorpFormal Verification Engineer - New College Grad 2026Santa Clara, CAYou will employ advanced formal techniques to obtain sufficiently bounded proofs while working with architects, designers, and pre- & post-silicon verification teams to accomplish your tasks. Come, join our GPU Formal Verification team and help build the real-time, cost-effective computing platform driving our success in this exciting and quickly growing field.
Senior Verification Engineer NVIDIA CorpSenior Verification EngineerSanta Clara, CAStrong hands-on expertise in UVM, SystemVerilog, Verilog, Python, and C/C++, with a passion for root-causing complex issues; experience with constrained-random stimulus, functional coverage, assertion-based verification, and C/C++-based testbenches - ideally on shipped silicon. Domain knowledge of display pipelines: protocols (DisplayPort, HDMI, MIPI DSI/CSI), MMU interaction with ISO clients, and system low-power features (clock gating, power domains, retention, entry/exit sequences).
Design Verification Engineer, Principal Veracity Software IncDesign Verification Engineer, PrincipalSanta Clara, CAFull Name: Degree (BS/MS/PhD) – Major, University & Completion Year: Total Design Verification Experience (Years): Total SoC Verification Experience (Years): Experience leading Design Verification implementation and tape-out of complex SoCs (Yes/No – details): SystemVerilog Experience (Years – details): UVM Experience (Years – details): Experience writing detailed Verification Test Plans (Yes/No – details): Experience building Constrained Random Verification Environments (Yes/No – details): Experience with Coverage-Driven Verification & Coverage Closure (Yes/No – details): Experience with Python and/or Perl Scripting (Years – details): Experience using EDA Verification Tools (Specify tools): Experience with Object-Oriented Programming/Design (Yes/No – details): Linux Experience (Years – details): C++ Programming Experience (Years – details): ARM Assembly Experience (Yes/No – details): Experience with Multi-Core SoC Verification and Boot Code Verification (Yes/No – details): Experience leading verification teams or project-level verification activities (Yes/No – details): Understanding of Networking Protocols (Ethernet, TCP/IP, Switching, etc.) (Yes/No – details): Motivation / Reason for interest in this position: Contact Number: Email ID: LinkedIn Profile URL: Full Address (Street, City, State, Zip Code): Notice Period: Current Work Authorization Status: Expected Salary: Are you able to relocate on your own expenses and work Santa Clara, CA - Onsite?. · BS Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of verification and firmware and software development experience (or MS/PhD with 5+ years experience).
Soc Asic Verification Engineer - New College Grad 2026 NvidiaSoc Asic Verification Engineer - New College Grad 2026Santa Clara, CANVIDIA is seeking to hire a verification engineer to verify the world's most powerful SoCs with AI capabilities for self-driving cars, gaming consoles & other automated machines (see https://www.nvidia.com/en-us/data-center/vera-cpu/ The base salary range is 100,000 USD - 166,750 USD for Level 1, and 116,000 USD - 189,750 USD for Level 2.
Senior Verification Engineer - Hardware NVIDIA CorpSenior Verification Engineer - HardwareSanta Clara, CAWhat you will be doing: We support multiple emulation environments using the latest emulation techniques (C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, Accelerated UVM Testbenches). NVIDIA invention of the GPU in 1999 accelerated the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing.
System Verification Engineer NVIDIA CorpSystem Verification EngineerSanta Clara, CAWhat you will be doing: We support multiple emulation environments using the latest emulation techniques (C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, Accelerated UVM Testbenches). What we need to see: M.S or equivalent experience in Electrical Engineering, Computer Science, Computer Engineering or related field with 4+ years of proven experience.
Senior System Verification Engineer NvidiaSenior System Verification EngineerSanta Clara, CAWhat you will be doing: We support multiple emulation environments using the latest emulation techniques (C/C++ DPI Transactors, SV assertions, Coverage, Power Estimation, SpeedBridges, Accelerated UVM Testbenches). What we need to see: M.S or equivalent experience in Electrical Engineering, Computer Science, Computer Engineering or related field with 8+ years of proven experience.