div>The pay range for this role is an estimate based on a wide range of compensation factors, inclusive of base pay only.
Headquartered in Dublin, Ohio (USA) with Engineering Centers in Pune, India and Yokohama, Japan, Goken is a global Engineering Services and Product Development company founded in 2004.
All of which is driven by a world-class vertically integrated engineering team, spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW engineering. You will interact with the analog/RF design team, digital DV team digital design team, and wireless system team to develop best-in-class verification methodologies that ensure silicon-correct functionality with optimal coverage and time-to-tapeout trade-off.
Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in-class UVM Testbenches, implement effective coverage driven and directed test cases, deploy new AI tools, and implement methodologies to improve quality of tape-out readiness. This position comes with responsibility for pre-silicon RTL verification of block and top-level SOC, all aspects of SOC Design Verification engineering, and will enable you to thrive in a dynamic multi-functional organization, debate ideas openly, and deliver on complex Wireless protocol chip requirements.
El Segundo, CA18 days ago
Your work will contribute to the development of cutting-edge defense solutions across Mission Systems, leveraging your expertise in chip-level verification methodologies of a wide variety of high-performance digital FPGAs & ASICs. Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 5 years prior relevant experience or an Advanced Degree in a related field and minimum 3 years of experience.
Costa Mesa, CA20 days ago
p>To ensure your safety and help you navigate your job search with confidence, please keep the following critical points in mind: No Financial Requests: Anduril will never solicit payment or demand personal financial details (such as banking information, credit card numbers, or social security numbers) at any stage of our hiring process. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.
p>The Digital Verification Engineer will work closely with design teams to validate digital circuit implementations, develop test benches, perform functional verification preparing Manufacturing/tester patterns and debug of failing tests. xa0 xa0 xa0 xa0 xa0 xa0 xa0(For more details on TSMC's Core Values, please visithttps://www.tsmc.com/english/aboutTSMC/values).
and/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing (CDL drivers only), vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training. Required for Certain Job Profiles: Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10,001 lbs.
and/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing (CDL drivers only), vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training. Required for Certain Job Profiles: Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10,001 lbs.
p>Your key responsibilities will include but not be limited to: - Perform end-to-end analog/mixed-signal verification of RF Front End Modules (FEM), from block-level through full-chip integration, leveraging schematic, behavioral, and functional views to achieve comprehensive coverage while meeting project schedules. In this role, you will play a critical part in developing and advancing industry-leading AMS verification methodologies, defining scalable workflows, and selecting best-in-class tools to enable zero-defect product development while meeting competitive project schedules.
El Segundo, CA30+ days ago
Develop state-of-the-art UVMf-based top-level and module-level testbenches using block-to-top best practices for reusability, including both control and data plane stimulation using VIP & System Verilog DPI-C integration with existing MATLAB and Python numerical models. Please Note: To conform with the United States Government Space Technology Export Regulations, the applicant must be a U.S. citizen, lawful permanent resident of the U.S., conditional resident, asylee or refugee (protected individuals as defined by 8 U.S.C. 1324b(a)(3)), or eligible to obtain the required authorizations from the U.S. Department of State.
El Segundo, CA25 days ago
li>Develop state-of-the-art UVMf-based top-level and module-level testbenches using block-to-top best practices for reusability, including both control and data plane stimulation using VIP & System Verilog DPI-C integration with existing MATLAB and Python numerical models. Please Note: To conform with the United States Government Space Technology Export Regulations, the applicant must be a U.S. citizen, lawful permanent resident of the U.S., conditional resident, asylee or refugee (protected individuals as defined by 8 U.S.C. 1324b(a)(3)), or eligible to obtain the required authorizations from the U.S. Department of State.
Your key responsibilities will include but not be limited to: Perform end-to-end analog/mixed-signal verification of RF Front End Modules (FEM), from block-level through full-chip integration, leveraging schematic, behavioral, and functional views to achieve comprehensive coverage while meeting project schedules. In this role, you will play a critical part in developing and advancing industry-leading AMS verification methodologies, defining scalable workflows, and selecting best-in-class tools to enable zero-defect product development while meeting competitive project schedules.
Costa Mesa, CA30+ days ago
p>To ensure your safety and help you navigate your job search with confidence, please keep the following critical points in mind: No Financial Requests: Anduril will never solicit payment or demand personal financial details (such as banking information, credit card numbers, or social security numbers) at any stage of our hiring process. You will lead verification strategy and methodology for FPGA/SoC designs on AMD (Xilinx) platforms for flight-critical avionics, owning UVM-based methodology, coverage-driven verification, and the roadmap for verification tooling across our programs.
Long Beach, California19 days ago
p>JetZero is seeking an experienced Flight Control Laws Validation & Verification (V&V) Engineer to support the development, verification, and validation of advanced flight control laws for the BWB Demonstrator. This is only going to increase: Air travel is forecasted to double by 2050, while meaningful efficiency gains using current airplanes have hit a wall.
As part of the COE, you will design, verify, and deliver IP subsystem building blocks powering Marvell''s most advanced custom chips for hyperscale cloud, AI, and data center customers - working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
The SoC family of multi-core CPU processors and Radio Access SoCs offer best-in-class performance, low power, rich software ecosystem, virtualization features, and open source application support with highly optimized custom ARM CPU cores providing an excellent solution for a highly flexible end-to-end optimized 5G platform. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
and/or transports placardable amounts of hazardous materials by ground in any vehicle on a public road while in commerce, may be subject to additional Federal Motor Carrier Safety Regulations including: Driver Qualification Files, Medical Certification (obtained before onboarding), Road Test, Hours of Service, Drug and Alcohol Testing (CDL drivers only), vehicle inspection requirements, CDL requirements (if applicable) and hazardous materials transportation/shipping training. Required for Certain Job Profiles: Drivers who operate Commercial Motor Vehicles with a Gross Vehicle Weight (GVW), Gross Vehicle Weight Rating (GVWR) or combination of power unit and trailer that meets or exceeds 10,001 lbs.
li>Collaborating closely with architecture and RTL teams to specify properties, resolve complex issues in building, and influence micro-architecture decisions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.
You will also be eligible for equity and benefits.
p>• BS/MS/PhD or equivalent experience in CS/CE/EE • 12+ years in ASIC verification with 8+ years focused on formal verification methods • Mastery of SystemVerilog Assertions (SVA) and formal property verification • Proficient on at least one popular formal verification tool in the industry (JapserGold, VC Formal, etc.) • Good scripting skills for flow automation (tcl, python, etc.) • Good written and oral communication skills • Keen attention to details. You will employ sophisticated formal techniques to acquire sufficiently bounded proofs while working with architects, designers, and pre- & post-silicon verification teams to accomplish your tasks, as well as improve formal verification methodologies and flows.
p>What we need to see: • Bachelors Degree in EE, CS or CE (or equivalent experience) and 8+ years of relevant industry experience • Background with building block and SoC level testbench utilizing strong debugging and analytical skills • Experience in verification using random stimulus along with functional coverage, assertion-based verification methodologies and tools • Expertise in SystemVerilog and Universal Verification Methodology (UVM) • Experience with design and verification tools (VCS, Verdi or equivalent) • Background in UPF power verification is a plus • Experience in netlist and DFT verification is a plus • Perl/Python and C/C++ programming language experience desirable • Knowledge of ASIC design flow, from specification to GDS • Knowledge of applying machine learning to ASIC verification flow.
What youll be doing:
• As a key member of our ASIC Verification team, you will verify the design and implementation of inference accelerator • You will be responsible for verification of the ASIC design, architecture, reference models and micro-architecture using advanced verification methodologies • Understand the design and implementation of your unit, define the verification scope, develop the verification infrastructure and verify the correctness of the design • Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks • Implement and optimize automated verification flows to improve productivity and efficiency • Stay updated on the latest trends and advancements in ASIC design verification and incorporate innovative techniques into the verification process.
p>Job Description: We are looking for highly skilled and efficient Design Verification engineers that want to verify new designs that can evolve rapidly over the next several generations in a very dynamic market using industry-proven constrained random methodologies with System Verilog and UVM.
Be part of developing our next-generation product in a series of high-throughput Ethernet products that deliver unprecedented performance at critically important power efficiency.
Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. These chips use cutting-edge technology to facilitate data transfers at high speeds, and you will help verify that each design meets our customers' specifications whether they're a major telecom organization or automotive company, etc.
The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies. The Role:
Be part of Amazon Leo's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways.
Irvine, California30+ days ago
What You Bring: Bachelor’s or Master’s degree in Robotics, Electrical Engineering, Computer Engineering, Computer Science, Mechanical Engineering, or a related technical field.
FieldAI’s Irvine team is where embodied AI meets real robots, real sensors, and real field deployments.
El Segundo, California30+ days ago
p style="text-align:inherit"/>As part of our commitment to maintaining a secure hiring process, candidates may be asked to attend select steps of the interview process in-person at one of our office locations, regardless of whether the role is designated as on-site, hybrid or remote..
Hired applicants may be eligible for annual short-term and/or long-term incentive compensation programs depending on the level of the position and whether or not it is covered by a collective-bargaining agreement.
Costa Mesa, CA30+ days ago
p>To ensure your safety and help you navigate your job search with confidence, please keep the following critical points in mind: No Financial Requests: Anduril will never solicit payment or demand personal financial details (such as banking information, credit card numbers, or social security numbers) at any stage of our hiring process. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.
El Segundo, CA30+ days ago
li>Experience with system issues associated with RF design such as Noise Figure, Linearity, S-Parameters, Antenna Gain, Antenna Directivity, Output Power, Side Lobe Levels, Rogue Oscillations, etc. What You Will Do:
We are seeking an experienced Principal Electrical Engineer- Antenna Test and Verification specializing in RF/Microwave and Antenna / Active Electronically Scanned Array (AESA) Integration and Testing.