UNKNOWN

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AI Chip Engineering Digital IP team defines and develops components for a wide range of products, including automotive microprocessors, application processors, microcontrollers, and networking. The Austin Digital IP team develops components for DDR, Display Controller, high-speed serial links, cores, memory controllers, and interconnect.

NXP Semiconductors NV

Senior Digital Design Engineer

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Lead physical implementation, from floorplanning through tapeout, including physically-aware, ultra-low-power logic synthesis, place-and-route, static timing analysis, and EM/IR, at all levels of the SoC hierarchy Define physical design methodology and flows to realize power and timing intent, and in doing so, meet milliwatt-level always-on power budgets in a wearable form factor, where thermal limits demand perf/mW compute efficiency Identify and resolve physical implementation bottlenecks related to congestion, timing, and power; then develop automation and AI-assisted flows to improve throughput and QoR Collaborate with RTL designers to provide implementation feedback that shapes the microarchitecture towards power- and area-efficient timing closure Work closely with package engineers to ensure the floorplan, clock tree, and power plan meet the product-level power delivery, signal integrity, thermal, and routability requirements Partner with design verification and DFx teams to ensure physical implementation supports gate-level functional correctness and meets debug and testability requirements Drive EDA vendor engagement, tool evaluations, and flow improvementsBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience Bachelor's degree in Electrical Engineering, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of experience in SoC or ASIC physical design Hands-on RTL-to-GDSII experience in 3nm or below, including floorplanning, physical synthesis, placement, clock tree synthesis, routing, static timing analysis, and signoff Experience with low-power implementation techniques, including power gating, voltage areas/islands, UPF, and DVFS Experience with static timing analysis, including defining timing constraints, exceptions, and PVT corners/modes for functional and DFT signoff, and accounting for OCV/POCV and crosstalk effects Experience working with EDA tools such as Fusion Compiler/Genus, ICC2/Innovus, PrimeTime/Tempus, RedHawk/Voltus, or equivalent Proficiency in scripting (TCL, Python, or Perl) and reading Verilog netlists/RTL Experience collaborating across RTL, DV, DFx, package, and vendor teams Ownership of block-level and/or full-chip power grid planning: dedicated macro supplies, power-switch chaining, MiM/decoupling caps, and EM/IR closure Track record of defining signoff criteria and leading tapeout execution Tapeout experience at 3nm or below Experience adhering to and implementing responsible, ethical AI practices (e.g. prompt/context engineering, agent orchestration) and staying current with emerging AI technologies Background in physically-aware synthesis of ultra-low-power designs, including custom recipes and app options, low-voltage PPA exploration, and UPF authoring Management of the die area budget, including full-chip partitioning, beachfront allocations, channel planning, and pipeline/feedthrough insertion Facility with advanced clock-tree synthesis, such as multi-source / H-tree, at block- and/or chip-level, including clock power reduction and hierarchical techniques Experience leading chip-level timing closure across multi-corner/multi-mode scenarios, authoring I/O timing constraints, parsing flat timing reports, and implementing timing ECOs Experience with 3D-IC structures (e.g., TSVs), EDA tools, and signoff methodologies Master's or PhD degree in Electrical Engineering, Computer Engineering, or equivalent areaMeta builds technologies that help people connect, find communities, and grow businesses.

Meta Platforms Inc

SoC Physical Design Engineer

As a Physical Design Engineer, you will translate RTL designs into optimized silicon implementations, working across floorplanning, placement, clock tree synthesis, routing, and signoff to deliver high-performance, power-efficient chips. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today-beyond the constraints of screens, the limits of distance, and even the rules of physics.

Physical Design Engineer, Reality Labs Silicon

As a Mechanical Design Engineer for the Die Shop, you will specialize in casting flow and thermal simulations, and will work in the team that designs Tesla's Giga Casting dies. The Die Shop is part of the Materials Engineering group responsible for the build, launch and handover of Tesla's high pressure die casting dies, used for vehicle programs.

Tesla Inc

Sr. Mechanical Design Engineer, Flow Simulations, Die Shop

Founded in 2020, WRITER is backed by investors including Insight Partners, ICONIQ, Radical Ventures, Premji Invest, Balderton, B Capital, Salesforce Ventures, Adobe Ventures, Accenture, Citi Ventures, IBM Ventures, WndrCo, and others. Experience with AI product surfaces - tool-call UIs, streaming responses, agent state, and dynamic UI rendering - and comfort navigating ambiguous, cross-team problems with good judgment about when to loop others in.

Writer Inc

Design engineer (US)

A consistent track record of delivering large, sophisticated designs in high volume production for low power applications Solid working experience with synthesis, power, performance and verification teams to develop and deliver high quality RTL design on time Strong interpersonal skills, as the candidate will work with diverse groups within the company Self-starter, highly motivated, highly organized, and schedule driven Familiarity with all front-end tools including lint, CDC, synthesis. This is a high transparency and critically important role and requires close working relationships with many groups and an organized approach to coordinate all tasks in parallel to hit schedules consistently with a quality design.

<div class="col-md-4 passion" style="background-color: #666666; border-radius: 20px; -webkit-box-shadow: 2px 2px 2px 2px #979b91; -moz-box-shadow: 2px 2px 2px 2px #979b91; box-shadow: 2px 2px 2px 2px #979b91; color: #ffffff; font-family: calibri; font-size: 13px; padding: 17px; text-align: center;">
<h3 style="color: #ffffff; font-size: 16px; font-weight: normal;">We bring amazing people together to make amazing things happen.</h3>
<p>We’re a diverse collection of thinkers and doers, continually reimagining what’s possible to help us all do what we love in new ways. The people who work here have reinvented entire industries with the Mac, iPhone, iPad, and Apple Watch, as well as with services, including iTunes, the App Store, Apple Music, and Apple Pay. And the same passion for innovation that goes into our products also applies to our practices — strengthening our commitment to leave the world better than we found it.</p>
</div>
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<h3 style="color: #666666; font-weight: 500;">About Apple</h3>
<p>There’s a place here for every kind of brilliant.
Everyone here is an innovator, or an innovator-to-be, no matter what your team or your role. So bring your passion, courage, and original thinking and get ready to share it, because every new product, service, or feature we invent is the result of people working together to make each others’ ideas stronger. Innovation at this level depends on people who represent the variety of the human experience and inspire us with their own fresh perspectives. Together, we’ll do amazing work that can make a difference in people’s lives. Including your own.

<a href="https://www.apple.com/jobs/us">Learn more about working at Apple.</a>
</p>
</div>

Apple Inc

ASIC Design Engineer - Fabric/Interconnect

In this role as a Custom Circuits DV Engineer, you will be working with the digital custom circuits team to ensure that all pre-silicon deliveries of custom IPs to all Apple SoC's are bug-free. In this highly visible role, you will be at the center of a SoC design effort collaborating with all teams, with a critical impact on getting bug-free functional products to market quickly.

Custom Circuits Design Verification Engineer

Maximize PPA: Optimize layout topologies to maximize cell density and utilization, architecting robust power delivery networks (PDN) to minimize IR drop and meet aggressive frequency targets on advanced foundry nodes. Proven track record running logic synthesis, integrating compiled memory macros, and managing multi-voltage design techniques using power intent specifications (UPF/CPF).

YEAR

River AI

Physical Design Engineer, Hardware

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Demonstrated experience applying AI/ML techniques in engineering workflows — this could include using LLMs for code generation and debugging, building ML-assisted design analysis tools, or integrating AI-assisted flows into EDA environments. This role is a rare opportunity to craft production-grade EDA tooling that operates at the bleeding edge of packaging technology, where no commercial solution exists yet and the problems you solve become the new industry baseline.

<p><strong>Visualize your future . . . We Do</strong><br>
NVIDIA is the world leader in graphics processing technologies, creating innovative, industry-changing products for computing, consumer electronics, and mobile devices. NVIDIA products are transforming visually-rich applications such as video games, film production, broadcasting, industrial design, space exploration, and medical imaging. We invest in our people and our technologies, support and fund industry research around the world, and consistently deliver high-quality products. NVIDIA's culture promotes and inspires a team of world-class employees to be at the top of their game. We've created an environment where talents are recognized and collaboration is valued. Our employees are shaping the world of tomorrow. . . today. We invite you to explore the opportunities available at NVIDIA to see what your future may hold.</p>

NVIDIA

Package Design Methodology Engineer

For this position, you should have real passion for verification methodologies and implementation that enable high quality system-level IP design and robust verification at multiple environment levels (e.g., unit, sub-system, and SOC). The expected base salary ranges for this position are:116,000 USD – 189,750 USD for Level 2; and 136,000 USD – 218,500 USD for Level 3.

ASIC Design Verification Engineer - New College Grad 2026

For this position, you should have real passion for verification methodologies and implementation that enable high quality system-level IP design and robust verification at multiple environment levels (e.g., unit, sub-system, and SOC). In this position you will have the chance to create a high-level and broad impact at NVIDIA working on a system-level IP responsible for measuring performance on multiple projects.

Nvidia

Asic Design Verification Engineer - New College Grad 2026

Collaborating with RTL designers, architects, and verification colleagues, you will investigate complex issues, support verification closure for assigned features, and contribute to the delivery of high-quality IP. Practical experience verifying ASIC or SoC designs using SystemVerilog and UVM, including constrained-random testing, assertions, scoreboards, and functional coverage.

ARM Ltd

Design Verification Engineer - Memory Controller IP

Technical Tools & Development Fluency: Hands-on experience with Figma, Git-based version control (GitHub, Bitbucket, or equivalent), modern AI-assisted development tools such as Claude Code, Cursor, Copilot, or similar, and front-end technologies such as React, TypeScript/JavaScript, HTML, and CSS. Connect Tools and Capabilities: Use APIs, MCPs, skills, agents, and integrations to connect tools and information, remove unnecessary manual steps, and make common UX workflows easier to complete.

Genesys Cloud Services Inc

Senior UX Design Technologist

You will be the technical leader who takes this the rest of the way, partnering with electrical, mechanical, signal and power integrity, thermal, and manufacturing engineering, and with suppliers from concept through production - turning layout from a serialized, manual craft into a connected, model-driven, continuously validated discipline. Design, build, and deploy AI-assisted and agentic workflows for layout tasks such as constraint setup, design rule checking, design review, and manufacturing output generation - collapsing place DRC fix re-check loops that take hours today into seconds tomorrow.

Dell Technologies Inc

Hardware Senior Principal Engineer

Amphenol High Speed and Commercial Products Groups are the market leaders for high speed, high bandwidth electrical connectors for the Telecom/Datacom and Diverse markets (Mobile Networks, Storage, Servers, Routers, Switches, etc.). Amphenol Corporation is one of the world’s largest designers and manufacturers of electrical, electronic and fiber optic connectors and interconnect systems, antennas, sensors and sensor-based products and coaxial and high-speed specialty cable.

Amphenol TCS

Field Applications Engineer

AcquireTM

OTHER

build, digging into why organic traffic to a page collection dropped, shipping the component that makes that page type self-serve from then on, building an agent that reads an inbound RFP into a structured quote request, and setting the technical strategy for your platform. A big part of the job is building AI agents and automation that take work off people’s plates: agents that read inbound RFPs and turn them into structured records, that draft and route content, that automate the manual campaign and sales-ops processes people run by hand today.

Curative HR LLC

Software Engineer L2 - Growth Marketing Platform

Trinet ATS Feed

In this role, you'll collaborate with designers, engineers, and platform teams to build accessible, performant, and reusable components that power consistent experiences across multiple products and platforms. Hands-on experience or active experimentation with AI-enabled design systems, LLM context generation (e.g., custom instructions, rules, or system prompts for code assistants), or AI-driven UI workflows.

LEADING THE CHARGE INTO TOMORROW<br>
 
      AtGeneral Motors, we are passionate about earning customers for life.  This vision unites us as a team each and every day and is the hallmark of our customer-driven culture. In fact, there are a lot of exciting things to share about our company.  <br><br> Our story starts on November 18, 2010, when we completed the world’s largest initial public offering, emerging with a solid financial foundation that enables us to produce great vehicles for our customers and build a bright future for employees, partners and shareholders.Leading the way is our seasoned leadership team who set high standards for our company so that we can give you the best cars and trucks.

General Motors

Senior Design Engineer - GM Design System

Power Design: Design and route power delivery networks, accounting for current-carrying capacity, copper weight, and thermal reliefs for layouts of DC/DC converters, power switching circuits, and bus/rail distribution for optimal power integrity. Demonstrated experience designing and laying out power electronics: DC/DC converters, power planes, bus bars/high-current traces, thermal management, and power protection schemes (e.g., fusing, current limiting).

Apptronik

Senior PCBA Design Engineer

This role will own end-to-end physical design execution across complex designs, driving delivery from RTL to silicon for cutting-edge technology nodes. The ideal candidate demonstrates deep technical expertise to implement a given design on silicon with optimized quality and meeting PPA targets.

Tool Designer Jobs in Austin, TX

Senior Digital Design Engineer NXP Semiconductors NV

SoC Physical Design Engineer Meta Platforms Inc

Physical Design Engineer, Reality Labs Silicon Meta Platforms Inc

Sr. Mechanical Design Engineer, Flow Simulations, Die Shop Tesla Inc

Design engineer (US) Writer Inc

ASIC Design Engineer - Fabric/Interconnect Apple Inc

Custom Circuits Design Verification Engineer Apple Inc

Physical Design Engineer, Hardware River AI

Package Design Methodology Engineer NVIDIA

ASIC Design Verification Engineer - New College Grad 2026 NVIDIA

Asic Design Verification Engineer - New College Grad 2026 Nvidia

Design Verification Engineer - Memory Controller IP ARM Ltd

Senior UX Design Technologist Genesys Cloud Services Inc

Hardware Senior Principal Engineer Dell Technologies Inc

Field Applications Engineer Amphenol TCS

Software Engineer L2 - Growth Marketing Platform Curative HR LLC

Senior Design Engineer - GM Design System General Motors

Senior PCBA Design Engineer Apptronik

Principal Physical Design Engineer / Physical Design - ACE US NXP Semiconductors NV

Principal Physical Design Engineer NXP Semiconductor, Inc.

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