div>Our compensation reflects the cost of labor across several U.S. geographic markets, and we pay differently based on those defined markets.
Methodology Development: Invent and propagate best‑practice SIPI methodologies, including electromagnetic extraction, multi‑port S‑parameter modeling, and power‑network analysis for complex packaging environments.The actual annual salary offered will depend on several factors, including - among others - job-related skills, experience, technical expertise, qualifications, work location, and business needs. Expert-level RTL design skills (Verilog/SystemVerilog), with hands-on experience in synthesis, timing closure, and DFT concepts.
p>Required Background: - BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 12+ years of experience in functional verification of pipe-line based design preferably MLAs, DSPs, CPUs or GPUs.
- Good working experience of development of UVM and System Verilog Test Bench (BFMs, ScoreBoards, SVA etc. ) from scratch along with usage know how of debug & coverage tools.
Santa Clara, CA30+ days ago
Participate in the full design development cycle, end-to-end, from writing micro-architecture docs, RTL coding, specifications of timing, closely work with design verification teams to review test plans and execution of test, ability to bring up block tests on silicon during lab testing, and maintenance of designed blocks and reusable IPs. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.
Santa Clara, CA26 days ago
You will spend most of your time reviewing and shaping customer hardware designs - covering board architecture, PCB stack-up and material selection, power architecture, thermal design, mechanical integration, and reliability and retain full hands-on capability across the entire design lifecycle from architecture through schematic, layout guidance, and bring-up. As Senior Principal Engineer for Board & System Hardware Design, you will be the senior technical authority guiding customer hardware design-in on Marvell's Ethernet Switch and UALink platforms, and a key technical bridge between Marvell's silicon teams, internal hardware engineering, and the field.
Santa Clara, CA26 days ago
You will own layout guideline definition, post-silicon channel extraction and simulation, compliance testing, and SerDes tuning guidance, while also reviewing customer PDN designs and feeding learnings back to Marvell's silicon and hardware engineering teams as part of a continuous improvement loop. Note on experience level: While the years of experience above represent the typical bar for this role, exceptionally talented candidates with fewer years but demonstrated mastery - through impactful project work, deep technical contributions, or industry recognition - are strongly encouraged to apply.
Santa Clara, CA30+ days ago
What You Can Expect As a Principal Design Engineer, you will lead micro-architecture and RTL development and HW/SW co-design efforts working across multi-functional teams, in developing state-of-the-art designs for the up and coming CXL product roadmap. Expected Base Pay Range (USD) 158,600 - 237,600, $ per annum The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.