Design Verification Engineer (Silicon Engineering) Space Exploration TechnologiesDesign Verification Engineer (Silicon Engineering)Palo Alto, CA$135,000–$155,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Senior Design Verification Engineer Google LLCSenior Design Verification EngineerMountain View, CAApplyshare linkCopy linkemailEmail a friendMinimum qualificationsBachelors degree in Electrical Engineering Computer Engineering Computer Science a related field or equivalent practical experience.8 years of experience with verification methodologies and languages such as UVM and SystemVerilog. Experience with different verification techniques and methodologies including formal GLS UPF based Power simulations UVM and C based testing etc. to achieve bug-free Silicon in complex SoCs.
Silicon Design Verification Engineer-FPGA/System Verilog Advanced Micro Devices, IncSilicon Design Verification Engineer-FPGA/System VerilogSan Jose, CaliforniaYou will plan, develop, and execute comprehensive verification strategies across complex digital subsystems, working closely with cross-functional engineering teams to deliver robust, bug-free designs. You bring strong analytical and debugging skills, communicate effectively across globally distributed teams, and are motivated to learn new technologies while taking ownership of difficult problems.
Digital Verification Engineer - 1999764 Ethan Alexander GroupDigital Verification Engineer - 1999764Campbell, CaliforniaProficiency in verification test planning, test bench architecture, assertions, problem solving and debugging. Debug/triage automated regressions, run gate level simulations, and perform coverage analysis.
NewSr. FPGA Design & Verification Engineer Dolby Laboratories IncSr. FPGA Design & Verification EngineerSan Francisco, CA$137,100–$188,300 / yearDolby's consumer entertainment and cinema businesses are bringing Dolby's breakthrough technologies, powering the world's top movies, TV shows, music, games, and live sports to more places around the world across a wider range of consumer experiences and devices. Using disciplined engineering practices such as coverage-driven verification, design automation, and continuous process improvement, youll help deliver the quality and reliability that define Dolbys industry-leading cinema products.
Verification Engineer - Aeromechanical (Design & Test) PivotalVerification Engineer - Aeromechanical (Design & Test)Palo Alto, California$115,000–$145,000 / yearDemonstrates a proactive safety mindset by embedding safety into daily operations, identifying and mitigating risks through assessments and training, encouraging open dialogue on safety concerns, and continuously improving protocols to ensure a safe work environment. Actively seeks and values diverse stakeholder perspectives, builds cross-functional relationships, and fosters trust through empathetic, fact-based communication—committing to shared decisions for the greater good.
SoC Verification Engineer – NoC / UVM Advanced Micro Devices, IncSoC Verification Engineer – NoC / UVMSan Jose, CaliforniaExperienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subsystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs. .
Senior Design Verification Engineer Intel Corp.Senior Design Verification EngineerSanta Clara, CA$164,470–$311,890 / yearAdditional Locations: Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). Experience in interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; cache coherency and memory consistency models.
SoC Verification Engineer - NoC / UVM Advanced Micro Devices IncSoC Verification Engineer - NoC / UVMSan Jose, CAPREFERRED EXPERIENCE: Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs.
Senior Design Verification Engineer - Physical AI Compute AuradineSenior Design Verification Engineer - Physical AI ComputeSanta Clara, CA$200,000–$500,000 / yearYou will work alongside experienced leaders, architects, engineers, and operators who have delivered industry-defining products across mobile, cloud, semiconductor, and AI platforms. You will help establish confidence in the correctness, performance, reliability, and safety of the architecture-from individual RTL blocks to complete HW/SW systems running real-world workloads.
CPU Processor Performance Verification Engineer Apple IncCPU Processor Performance Verification EngineerSanta Clara, CAWork closely with OS and compiler teams on system and application performance tuningMinimum BS Academic experience with performance modeling, processor verification, or RTL design Academic experience in digital logic design, CPU architecture, and microarchitecture Experience in at least one of the following: assembly, C/C++, Verilog, or System VerilogExperience in developing performance test plans and writing/debugging assembly tests for performance correlation and verification Experience in benchmark and workload analysis and CPU performance profiling Knowledge of compiler techniques and OS for performance optimization Knowledge in developing instruction profiling tools on silicon Experience in performance modeling for advanced CPU designs Experience in silicon validation Ability to work across teams to optimize silicon performance Should be a great teammate with excellent communication and presentation skills and able to work independently on the owned unit. As a CPU Processor Performance Verification Engineer owning the verification of a certain area of performance features in a chip design, you will have responsibilities as follows: Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon).
Product Verification Engineer Varian Medical Systems IncProduct Verification EngineerPalo Alto, CA$115,980–$159,478 / yearIt is Siemens Healthineers' policy to comply fully and completely with all United States export control laws and regulations, including those implemented by the Department of Commerce through the Export Administration Regulations (EAR), by the Department of State through the International Traffic in Arms Regulations (ITAR), and by the Treasury Department through the Office of Foreign Assets Control (OFAC) sanctions regulations.". You will be responsible for writing and executing testing cases and doing UI automated tests using our in-house developed python testing framework to test our latest radiotherapy systems.
NewProduct Verification Engineer (SW/HW) Varian Medical Systems IncProduct Verification Engineer (SW/HW)Palo Alto, CA$139,180–$191,378 / yearIt is Siemens Healthineers' policy to comply fully and completely with all United States export control laws and regulations, including those implemented by the Department of Commerce through the Export Administration Regulations (EAR), by the Department of State through the International Traffic in Arms Regulations (ITAR), and by the Treasury Department through the Office of Foreign Assets Control (OFAC) sanctions regulations.". You will be responsible for writing and executing testing cases and doing UI automated tests using our in-house developed python testing framework to test our latest radiotherapy systems.
NewASIC Verification Engineer Hewlett Packard EnterpriseASIC Verification EngineerSunnyvale, CaliforniaPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.
NewSenior ASIC Verification Engineer Hewlett Packard Enterprise CoSenior ASIC Verification EngineerSunnyvale, CA$153,500–$310,500 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
ASIC Verification Engineer Hewlett Packard Enterprise CoASIC Verification EngineerSunnyvale, CA$120,000–$243,000 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
CPU Verification Engineer (Multiple Locations) Qualcomm IncCPU Verification Engineer (Multiple Locations)Santa Clara, CA$167,100–$250,700 / yearDeep knowledge of Micro-Processor Verification functions and Architectures, in domains such as: Cache Coherence, Memory ordering and Consistency, Prefetching, Branch Prediction, Renaming, Speculative execution, and Address Translation/Memory Management. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
NewSenior ASIC Verification Engineer Hewlett Packard EnterpriseSenior ASIC Verification EngineerSunnyvale, CaliforniaPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world.
NewSenior Asic Verification Engineer Hewlett Packard EnterpriseSenior Asic Verification EngineerSunnyvale, CA$153,500–$310,500 / yearPlease note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today's complex world.
Senior Design Verification Engineer MythicSenior Design Verification EngineerPalo Alto, CA$120,000–$225,000 / yearDesign Verification at Mythic: At Mythic, our Design Verification (DV) team is central to ensuring the correctness and reliability of our novel digital dataflow architecture, which includes a sophisticated scheduling subsystem, high-performance interconnect fabric, and advanced DMA engines that work together with our Analog Compute Engines to accelerate AI workloads. Because today's AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently.
Design Verification Engineer MythicDesign Verification EngineerPalo Alto, CA$120,000–$225,000 / yearBecause today's AI workloads are too large and intricate to be fully verified in hardware alone, our team takes creative and rigorous approaches-combining simulation, modeling, and innovative verification strategies-to prove that neural networks will function correctly and efficiently. We've raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets.
Senior Design Verification Engineer, Silicon Google LLCSenior Design Verification Engineer, SiliconMountain View, CAExecute gate-level simulations (GLS) and Unified Power Format (UPF)-based power simulations, performing debugging to deliver high-performance and low-power hardware. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement.
Staff ASIC Design Verification Engineer Google LLCStaff ASIC Design Verification EngineerSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing with key teams working on the development of our TPUs Vertex AI for Google Cloud Google Global Networking Data Center operations systems research and much more. Were the driving force behind Googles groundbreaking innovations empowering the development of our cutting-edge AI models delivering unparalleled computing power to global services and providing the essential platforms that enable developers to build the future.
Sr. ASIC Design Verification Engineer Silicon Engineering Space Exploration Technologies CorpSr. ASIC Design Verification Engineer Silicon EngineeringPalo Alto, CA$175,000–$280,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Principal Design Verification Engineer Silicon Engineering Space Exploration Technologies CorpPrincipal Design Verification Engineer Silicon EngineeringSunnyvale, CA$210,000–$310,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Staff Physical Verification Engineer, AI Hardware Tesla IncStaff Physical Verification Engineer, AI HardwarePalo Alto, CA$128,000–$414,000 / yearBy creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. Tesla's AI Hardware Team is looking for experienced, highly skilled VLSI engineers who enjoy working across the logic, circuit, methodology, and physical design levels.
Applied ML - Functional Verification Engineer Cadence Design Systems IncApplied ML - Functional Verification EngineerSan Jose, CA$114,800–$213,200 / yearCadence customers are the worlds most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. You will collaborate closely with a highly skilled team of machine learning engineers experienced in training large language models at scale, as well as accomplished software engineers with proven expertise in product development and deployment.
Full-Chip Physical Design Verification Engineer TenstorrentFull-Chip Physical Design Verification EngineerSanta Clara, CAAs the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. Strong background in ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM), with solid understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges.
Full-Chip Physical Design Verification Engineer Tenstorrent IncFull-Chip Physical Design Verification EngineerSanta Clara, CAAs the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. Strong background in ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM), with solid understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges.
Senior Silicon Design Verification Engineer, YouTube Video Accelerators Google LLCSenior Silicon Design Verification Engineer, YouTube Video AcceleratorsMountain View, CAAs a part of the Design Verification (DV) role in the Argos IP team, you will ensure the functional correctness of custom video codec ASICs for YouTube by managing a specialized High-Level Synthesis (HLS) workflow that requires verification at both the C/C++ and RTL levels. You will be responsible for bridging the gap between algorithmic intent and hardware implementation, employing a hybrid strategy that includes C++ software testing, C/RTL co-simulation, and traditional SystemVerilog/ Universal Verification Methodology (UVM) testbenches to guarantee equivalence and compliance.
Design Verification Engineer BaiduDesign Verification EngineerSunnyvale, CaliforniaYou will help on UVM Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development. Work closely with the design and systems engineering teams to review specifications and architecture, extract features, define verification plan & coverage model.
NewDesign Verification Engineer Veracity Ventures Inc.Design Verification EngineerSanta Clara, CAFull timeAs a leading member of the Network Switching team you will develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers and contribute to the methodology behind such development. · BS Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of verification and firmware and software development experience (or MS/PhD with 5+ years experience).
Design Verification Engineer Pyramid Consulting, IncDesign Verification EngineerSan Franscisco, CA$160,000–$170,000 / yearBS in Electrical Engineering / Computer Engineering and 8+ years of related experience or an MS in Electrical Engineering / Computer Engineering and 6+ years of related experience. By applying to our jobs you agree to receive calls, AI-generated calls, text messages, or emails from Pyramid Consulting, Inc. and its affiliates, and contracted partners.
CPU SoC Verification Engineer Google LLCCPU SoC Verification EngineerMountain View, CAGoogle is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement.
Design verification Engineer ApolisDesign verification EngineerSan Jose, CA$65–$70 / hourA bachelor’s degree in electrical or computer engineering, accompanied by a minimum of 8 years of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline. Key Skill: SV/UVM, AXI expertise, NOC/Crossbar, Performance.
Digital Verification Engineer Neuralink CorpDigital Verification EngineerSouth San Francisco, CA$131,000–$243,000 / yearThe team delivers architecture and logic implementation of digital modules with a strong focus in high-throughput low-power digital signal processing (DSP). These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.
Principal Silicon Design Verification Engineer Microsoft CorpPrincipal Silicon Design Verification EngineerMountain View, CA$142,800–$274,800 / yearPreferred Qualifications: Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR Masters Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR equivalent experience. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Masters Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
Design Verification Engineer Baidu USADesign Verification EngineerSunnyvale, CaliforniaYou will help on UVM Testbench development, directed/constrained random test generation, failure analysis and resolution, coverage analysis, and flow development. Work closely with the design and systems engineering teams to review specifications and architecture, extract features, define verification plan & coverage model.
Senior ASIC Verification Engineer (AI Hardware) 4 Staffing CorpSenior ASIC Verification Engineer (AI Hardware)San Jose, CaliforniaOur client an AI / Compute company of the verge of being the next Nvidia is looking for an experienced ASIC Verification Engineer to help ensure the quality, reliability, and performance of their next-generation AI-focused silicon. In this role, you'll partner closely with design, architecture, and software teams to validate complex hardware systems and contribute to cutting-edge compute solutions.
Sr. ASIC Design Verification Engineer (Silicon Engineering) SpaceXSr. ASIC Design Verification Engineer (Silicon Engineering)Palo Alto, CA$175,000–$280,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
Sr. Asic Design Verification Engineer (Silicon Engineering) Space Exploration TechnologiesSr. Asic Design Verification Engineer (Silicon Engineering)Palo Alto, CA$175,000–$280,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Principal Design Verification Engineer (Silicon Engineering) SpaceXPrincipal Design Verification Engineer (Silicon Engineering)Sunnyvale, CA$210,000–$310,000 / yearWe are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State.
Principal Design Verification Engineer (Silicon Engineering) Space Exploration TechnologiesPrincipal Design Verification Engineer (Silicon Engineering)Palo Alto, CA$210,000–$355,000 / yearITAR REQUIREMENTS: To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation).
Design Verification Engineer indie Semiconductor, Inc.Design Verification EngineerSan Jose, CAIf you''re passionate about groundbreaking technology and want to make a real impact alongside a fast-paced team that thrives on creativity and collaboration, we'd love to have you on board! As a Design Verification Engineer, you will be responsible for developing and executing comprehensive verification strategies for next-generation automotive camera video and vision processors.
CPU DFT Verification Engineer Apple IncCPU DFT Verification EngineerSanta Clara, CAWork with the silicon bringup team on developing tests that help the silicon bring up effortMinimum BS and 3+ years of relevant industry experience Experience in DFT design, DFT verification, or processor verification Experience with digital logic design, test/debug feature, or DFT architecture Experience with DFT and structural debug concepts and methodologies: JTAG, IEEE1500, or MBIST and scan Experience in scripting in Python, Perl, or TCLMaster's degree preferred Understanding of CPU architecture Experience in developing design verification test plans, test benches, and test vectors generation Experience with lab debug of CPUs/ASIC using built-in DFT and debug features is a plus In-depth knowledge in design verification environments like random constraint verification Knowledge of Verilog and experience with simulators and waveform debugging tools Should be an extraordinary teammate with excellent communication skills with the ability to articulate complex design issues during verification effort Be able to create and follow detailed work schedule and work independently on the verification efforts for a block/area of the design. In this highly visible role, you will be at the center of a chip design effort collaborating with all subject areas, with a critical impact on getting functional products to millions of customers quickly.
ASIC Design Verification Engineer, Technical Leader Cisco Systems IncASIC Design Verification Engineer, Technical LeaderSan Jose, CA$183,800–$263,600 / yearWho We Are: The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. For quota-based incentive pay, Cisco typically pays as follows: 75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and.
ASIC Design Verification Engineer, TPU GoogleASIC Design Verification Engineer, TPUSunnyvale, CAFrom software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.
NewSr. FPGA Verification Engineer Reliable Robotics CorporationSr. FPGA Verification EngineerMountain View, CaliforniaFPGA engineers at Reliable Robotics have a unique opportunity to work at the heart of a vertically integrated technology stack that goes all the way up to aircraft level, with a direct impact on the aircraft's capabilities and requirements. FPGA Verification Engineer, you will own the FPGA integration and test environment for multiple airborne products including their test benches & simulation, continuous integration, timing analysis, elemental analysis, and build.
Senior Formal Verification Engineer - AI Soc Development Intel Corp.Senior Formal Verification Engineer - AI Soc DevelopmentSanta Clara, CA$220,920–$311,890 / yearHarnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. As a Senior Formal Verification Engineer, you will play a critical role in ensuring the functional correctness of complex digital designs using advanced formal methods.
Design Verification Engineer - Soc Etched AIDesign Verification Engineer - SocSan Jose, CABacked by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads.