REQUIRED SKILLSMinimum total years of experience: 5-73+ years of hands-on experience in the design, simulation, and layout of PICs for visible or IR wavelengths on platforms such as Si, SiN, LiNbO, or BTO.3+ years of experience utilizing photonic device simulation and electromagnetic modeling tools for both component and circuit-level analysis (e.g., Lumerical FDTD/MODE/DEVICE, Ansys Photonics, Synopsys RSoft, or COMSOL Multiphysics).2+ years of experience with PIC layout tools and GDSII generation (e.g., KLayout, Cadence Virtuoso, gdsfactory, or equivalent), including familiarity with foundry PDK integration and design rule verification.2+ years of experience with scientific programming (e.g., Python or MATLAB) for scripting, design automation, and analysis.1+ years of experience supporting or executing PIC tapeouts at a commercial semiconductor foundry, including an understanding of fabrication process constraints (e.g., propagation losses, sidewall roughness, etch non-idealities).PREFERRED SKILLS3+ years experience in active PIC design, fabrication, and validation, particularly for visible wavelengths on LiNbO or BTO platforms.3+ years of experience in design space exploration, sensitivity analysis, and statistical performance/yield modeling for photonic circuits.3+ years of experience with one or more major photonic simulation tool suites (e.g., Lumerical, Synopsys, COMSOL, or equivalent).2+ years of experience utilizing photonic circuit-level simulation tools (e.g., Lumerical Interconnect, Synopsys OptSim, or VPIphotonics) for system-level performance evaluation.2+ years of experience in photonic device characterization and test, including both optical and electro-optic measurements.1+ years experience with fiber optics, free-space optics, PIC packaging, and comprehensive device characterization.1+ years experience with semiconductor fabrication processes and a deep understanding of process-induced performance limitations, such as optical losses, sidewall roughness, and process variability. Demonstrated ability to directly incorporate fabrication constraints into PIC designs (e.g., optimizing minimum feature sizes and bend radii, implementing effective tapering strategies, and using layout techniques to mitigate scattering and coupling losses).SUMMARYWe are seeking a passionate Optical Engineer to join our research and development team.