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Our high-speed IO infrastructure team develops the flows that keep large-scale ASIC development moving: integration automation, pre-submit qualification, build and verification infrastructure, operational metrics, and debug workflows. What You'll Be Doing: Apply practical AI workflows where they build leverage, including debug assistance, run triage, summarization, documentation, and workflow automation.

Visualize your future . . . We Do 
NVIDIA is the world leader in graphics processing technologies, creating innovative, industry-changing products for computing, consumer electronics, and mobile devices. NVIDIA products are transforming visually-rich applications such as video games, film production, broadcasting, industrial design, space exploration, and medical imaging. We invest in our people and our technologies, support and fund industry research around the world, and consistently deliver high-quality products. NVIDIA's culture promotes and inspires a team of world-class employees to be at the top of their game. We've created an environment where talents are recognized and collaboration is valued. Our employees are shaping the world of tomorrow. . . today. We invite you to explore the opportunities available at NVIDIA to see what your future may hold.

NVIDIA Corp

Senior ASIC Design Verification Infrastructure and Tools Engineer - GPU

More recently, GPU deep learning ignited modern AI - the next era of computing - with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. Experience with the following technologies is a huge plus: XLA, TVM, MLIR, LLVM, OpenAI Triton, deep learning models and algorithms, and deep learning framework design.

Senior Deep Learning Compiler Engineer - XLA

Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL. Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.

Nvidia

Asic Design Engineer - Clocks IP

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More recently, GPU deep learning ignited modern AI — the next era of computing — with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. This team is comprised of worldwide leading compiler engineering experts who provide leading edge performance and capabilities for NVIDIA's current and future complex parallel SIMT architectures.

NVIDIA

Senior Compiler Engineer - Backend GPU

Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.

ASIC Physical Design Engineer, Netlisting - New College Grad 2026

This role provides a unique opportunity to innovate at the cutting edge of process technology, EDA tools, and PD flows through collaboration with RTL, synthesis, DFT, foundry, timing other cross functional teams to push the limits of physical design at scale. We are looking for a physical design engineer to be a part of NVIDIA’s physical design (PD) methodology team driving innovation in PD across all of NVIDIA's products – Datacenter AI, HPC, Networking, Robotics, Autonomous driving, gaming and more.

Senior Physical Design Methodology Engineer, Innovus Flows

What you'll be doing: You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.

Senior Asic Physical Design Engineer, Netlisting

ASIC Design Engineer – Clocks IP

For this position, you should have real passion for verification methodologies and implementation that enable high quality system-level IP design and robust verification at multiple environment levels (e.g., unit, sub-system, and SOC). In this position you will have the chance to create a high-level and broad impact at NVIDIA working on a system-level IP responsible for measuring performance on multiple projects.

Asic Design Verification Engineer - New College Grad 2026

Your day could consist of debugging to get a process running in time for the market open, making a difficult on-the-spot decision that balances compliance, risk, and PnL during trading hours, or coordinating the technical rollout of a new trading strategy. Hudson River Trading (HRT) is looking for an Electronic Trading Support Engineer to join our global Trade Operations (TradeOps) team in NYC.

YEAR

Hudson River Trading LLC

Junior Electronic Trading Support Engineer

Through its robust suite of tools, Realtor.com not only makes a significant impact on the real estate industry at large, but for consumers, navigating the biggest purchase they will make in their life, by providing a user experience that is easy to use, easy to understand, and most of all, easy to make decisions. As a Staff SRE, you will be a strong technical contributor who implements best practices, solves complex problems, and enables our 200+ engineers to deliver exceptional customer experiences across our web and native application surfaces.

News Corp

Staff Site Reliability Engineer

More recently, GPU deep learning ignited modern deep learning - the next era of computing - with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. Building on open source software, designing and implementing data structures and UI interfaces to automate processes from equipment purchase to device config generation to deployment to operations.

Senior Software Engineer, Networking DGX Cloud

Demonstrated experience applying AI/ML techniques in engineering workflows - this could include using LLMs for code generation and debugging, building ML-assisted design analysis tools, or integrating AI-assisted flows into EDA environments. What we need to see: BS in Computer Science, Electrical Engineering, or a related field (or equivalent experience), and 5+ years of flow and methodology development experience building flows for interposer design used by engineering teams at scale.

Interposer Automation Engineer

The Hardware team at HRT builds high-performance compute engines using FPGA and ASIC technology to drive low-latency trading decisions on global markets. The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.

Hudson River Trading

Physical Design Engineer

The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits. For this position, you should have real passion for verification methodologies and implementation that enable high quality system-level IP design and robust verification at multiple environment levels (e.g., unit, sub-system, and SOC).

Senior Asic Verification Engineer

Drive rack-scale SW/FW architecture alignment across CSP engagements — including fabric management software, link health monitoring, GPU/NVSwitch error handling, SW/FW serviceability features (e.g., hot-plug support, component isolation, firmware-driven recovery), and multi-component firmware orchestration. Drive technical work streams with CSP engineering teams on rack-scale system software — ensuring they deeply understand fabric management, NVSwitch behavior, error handling and recovery policies, health telemetry APIs, and SW/FW-controlled recovery operation.

Principal Software Engineer, Rack-Scale System Software — CSP Engagements

What you'll be doing: Be an integral part of the team defining, developing, and delivering system-level methodologies and RTL to measure performance on the industry's leading GPUs and SOCs. What we need to see: BS or equivalent experience in Electrical Engineering, Computer Engineer, or related degree required, advanced degrees (MS, PhD) a plus.

Asic Design Engineer - Hardware

The base salary range is 152,000 USD - 241,500 USD for Level 3, and 184,000 USD - 287,500 USD for Level 4. You will also be eligible for equity and benefits. Collaborate and interact with other teams within NVIDIA, including compiler team as well as the CUDA driver team, to influence and design new features from the bottom up.

Senior Systems Software Engineer, CUDA and AI HW Profiler

You will work alongside our engineering, product, finance, FinOps, and operations teams to build a data platform that can connect these disparate data sources into a trusted view of how our infrastructure is used, what it costs, and ultimately how those costs contribute to the economics of our products. You will own the end-to-end implementation, starting with identifying the questions that matter, determining the data required to answer them, building the pipelines and models to make that data reliable and accessible, and finally turning it into insights that drive better decisions.

Sony Playstation Network

Data Engineer

You will work on critical platform systems including EKS infrastructure, Skyway (CI/CD), Frontdoor (Tyk API Gateway), Pantheon (Apollo GraphQL Federation), and our observability stack, while contributing to chaos engineering practices and cost optimization initiatives with measurable ROI. Through its robust suite of tools, Realtor.com not only makes a significant impact on the real estate industry at large, but for consumers, navigating the biggest purchase they will make in their life, by providing a user experience that is easy to use, easy to understand, and most of all, easy to make decisions.

Game Engineer Jobs in Austin, TX

Senior ASIC Design Verification Infrastructure and Tools Engineer - GPU NVIDIA Corp

Senior Deep Learning Compiler Engineer - XLA NVIDIA Corp

Asic Design Engineer - Clocks IP Nvidia

Senior Compiler Engineer - Backend GPU NVIDIA

ASIC Physical Design Engineer, Netlisting - New College Grad 2026 NVIDIA

Senior Physical Design Methodology Engineer, Innovus Flows NVIDIA

Senior Asic Physical Design Engineer, Netlisting Nvidia

ASIC Design Engineer – Clocks IP NVIDIA

Asic Design Verification Engineer - New College Grad 2026 Nvidia

Junior Electronic Trading Support Engineer Hudson River Trading LLC

Staff Site Reliability Engineer News Corp

Senior Software Engineer, Networking DGX Cloud NVIDIA Corp

Interposer Automation Engineer NVIDIA Corp

Physical Design Engineer Hudson River Trading

Senior Asic Verification Engineer Nvidia

Principal Software Engineer, Rack-Scale System Software — CSP Engagements NVIDIA

Asic Design Engineer - Hardware Nvidia

Senior Systems Software Engineer, CUDA and AI HW Profiler NVIDIA Corp

Data Engineer Sony Playstation Network

Sr Site Reliability Engineer News Corp

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