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ADAPTED_NOW

In this highly autonomous, customer-facing role, you will serve as a technical leader responsible for designing, integrating, and deploying advanced RF test systems for aerospace and defense customers. We are seeking a Senior RF Test System Engineer to join Aerospace & Defense Custom Solutions (ADCS) team.

Gables Search Group headquartered in Cleveland, Ohio has been a leader in search and placement nationwide since 2002.  Our company specializes in both direct and contract (temporary) staffing in all industries and disciplines.
At Gables Search Group, we connect exceptional professionals with outstanding organizations.  Our commitment to integrity, excellence, partnership, innovation, and respect sets us apart. With a personalized approach to recruitment, we ensure the perfect match between candidates and employers.
Whether you are a talented professional seeking new opportunities or an organization looking to build a high-performing team, Gables Search Group is here to guide you through the journey. Our success is built on the success of our clients and candidates, and we are dedicated to making a positive impact on the careers and businesses we serve.

Gables Search Group

RF Test System Engineer ( Loveland , Colorado ) 51745

Gables Search Group - Career Site

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Gilmour Space Technologies Pty Ltd

Mechanical Engineer II

Tenstorrent is seeking an Physical Design Engineer to lead cross-functional efforts to solve complex physical design challenges and develop end-to-end RTL-to-GDS methodologies across advanced nodes, with a strong focus on PPA and runtime improvements. The engineer will architect, integrate, and deploy AI/ML-driven solutions into production physical design flows, creating custom CAD tools and partnering with internal teams and EDA vendors to drive next-generation, ML-enabled capabilities.

Tenstorrent Inc

AI/ML Physical Design Flow Engineer

As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. I3C, UART), signoff breadth (DRC/LVS, EM/IR, LEC/Formality), multi-clock/CDC-aware implementation, PLL/DLL integration, and DFT-aware physical implementation (OCC/MBIST).

Physical Design Engineer, PnR

As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. Strong background in ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM), with solid understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges.

Full-Chip Physical Design Verification Engineer

As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).

Physical Design Engineer

FULL_TIME

The duties of the quality manager are to oversee quality operations, ensure excellent quality control of product and maintain and uphold the quality management system. Compensation for the position: MBK Machine would like to start the quality engineer position at a compensation rate of $30-41/hr (depending on technical knowledge, capability and experience) with a pay evaluation after 60 days of employment.

HOUR

MBK Machine

Quality Engineer

OTHER

Collaborate with Architecture, Physical Design, Verification, and Design-for-Test teams to design, document, implement, verify, and deliver high-performance Power, Clocking, Reset, and Control Fabric RTL optimized for timing, testability, manufacturability, and physical implementation. AMD's Core Complex Cache Hierarchy team builds the complexes that connect our compute (execution) cores — each complex combining multiple cores and their L2 caches together with a coherency fabric, optimized for the highest performance and power efficiency in the industry.

Advanced Micro Devices, Inc

CPU RTL Power, Clocking, Reset Design Engineer

[AW]-iCims

As a Project Engineer, you will assist the Project Manager with a variety of project related functions including planning and coordinating onsite construction activities for designated projects, to ensure that project objectives are accomplished within prescribed time frame and funding parameters. The construction industry changes rapidly, and we cultivate a dynamic workplace where even our newest team members can influence change and make an impact.

YEAR

US Engineering

Project Engineer - Innovations

IRecruitee

Tenstorrent

As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level.

Top Level Physical Design Engineer

ea_via_bold

As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. Use Python, Perl, and Tcl for automation and flow development; experience with SPICE, PNR, placement, CTS, routing, post-route optimization, DFT, or AI-based automation is a plus.

Physical Design Engineer, Timing

Physical Design Engineer, Pnr

Ai/Ml Physical Design Flow Engineer

Staff Engineer, Physical Design

As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. You'll collaborate closely with logic, DFT, and physical design teams to debug constraints, optimize paths, and ensure our chips meet performance targets across corners and modes.

Physical Design Engineer - STA

Our 1,500+ employees enjoy an active on-site experience from sporting activities (get in a few laps at lunch on our 1-mile walking path around campus, play ping-pong or volleyball, or stop in our 24- hour fitness center for a group or individual workout) to community service and many employee resource groups including Pride! We collaborate across engineering disciplines to implement features and functions for next-generation technologies, including HAMR (Heat Assisted Magnetic Recording), and define hardware and firmware architectures for future platforms.

Seagate Technology Holdings PLC

Firmware Engineer I

Typically requires a bachelors degree, masters degree or PhD in engineering or a related technical discipline from an accredited institution and progressive engineering experience as follows; nine or more years of experience with a bachelors degree, seven or more years of experience with a masters degree, or four or more years with a PhD. Ideal candidate has deep familiarity with payload design cycle from concept through manufacturing and deployment, hands-on experience in optical space payload ground-based alignment, test and integration, environmental test, and experience in optical system performance analysis, test plan development and execution.

Financial Manager Jobs in Oxnard, CA

RF Test System Engineer ( Loveland , Colorado ) 51745 Gables Search Group

Mechanical Engineer II Gilmour Space Technologies Pty Ltd

AI/ML Physical Design Flow Engineer Tenstorrent Inc

Physical Design Engineer, PnR Tenstorrent Inc

Full-Chip Physical Design Verification Engineer Tenstorrent Inc

Physical Design Engineer Tenstorrent Inc

Quality Engineer MBK Machine

CPU RTL Power, Clocking, Reset Design Engineer Advanced Micro Devices, Inc

Project Engineer - Innovations US Engineering

Full-Chip Physical Design Verification Engineer Tenstorrent

Top Level Physical Design Engineer Tenstorrent

Physical Design Engineer, Timing Tenstorrent

Physical Design Engineer, Pnr Tenstorrent

Ai/Ml Physical Design Flow Engineer Tenstorrent

Physical Design Engineer Tenstorrent

Staff Engineer, Physical Design Tenstorrent

Physical Design Engineer - STA Tenstorrent

Physical Design Engineer, Timing Tenstorrent Inc

Firmware Engineer I Seagate Technology Holdings PLC

Engineer V General Atomics

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