UNKNOWN

FEED

Physical Demands: Ability to lift a minimum of fifteen (15) pounds; Ability to exert maximum muscle force to lift, push, pull or carry; Ability to use abdominal and lower back muscles over time without fatigue; Ability to stand and/or sit for extended periods; Ability to bend, stoop, stretch, twist, sit, and reach; Fine motor skills; Good visual and auditory acuity. Translate visual brand systems into motion, conceptualizing and producing animated typography, title sequences, logo animations, transitions, lower thirds, information graphics, explainers, social video graphics, and video packaging that establish consistent brand behavior across platforms.

HOUR

KQED

Nabet On-Call Brand And Motion Graphics Designer / Designer 2

ea_via_bold

Conduct technical reviews and iterate on layout improvements with internal and external stakeholders Requirements for the Substrate Layout Designer include: 6 - 8+ years of experience in substrate layout design for high-performance IC packaging Proven experience expertise in organic substrate design from silicon to BGA Deep understanding of chiplet-based, multi-die, and advanced packaging (FPGA, CPU, CPU, MCM, CoWoS) Strong collaboration skills with ASIC, signal, and power teams Proficiency in Cadence Allegro APD, AutoCAD, or Siemens Xpedition. Collaborate with ASIC, signal integrity, and power teams to ensure clean escape routing and breakout strategies Evaluate routing feasibility in co-design environments, considering die floorplans and mechanical constraints.

YEAR

Zp Group Llc

Senior Substrate Layout Design engineer - 176158

Senior Substrate Layout Design engineer - 177107

Work effectively with cross-functional teams to ensure design requirements are met and provide feedback and solutions on the board level for the issues related to hardware, signal integrity/power integrity, mechanical, thermal, and manufacturing. Paid parental leave for all full time employees including 12 weeks paid parental leave for the birthing mother and 6 weeks paid parental leave for the non-birthing parent.

Lunar Energy

PCB Layout Engineer

This is a strategic technical leadership role for an experienced AMS layout leader who combines deep expertise in advanced-node analog layout, a strong understanding of high-speed PHY design challenges, and a proven track record of building and developing high-performing engineering teams. Responsibilities: Technical Leadership: Lead AMS layout engineering for advanced high-speed SerDes PHYs, driving physical implementation, optimization, and sign-off across critical analog and mixed-signal circuit blocks.

Upscale AI Inc

Senior Director, AMS Layout Engineering

You'll take multi-die 2.5D and 3D packages from bump map through tapeout release — defining substrate and interposer stackups, planning bump and ball maps against the die floorplan, routing high-density escape and HBM-class channels, and building the power delivery that feeds hundreds of amps into the accelerator. Exceptional abilities in advanced package physical layout: multi-die substrate and interposer routing, high-density escape, power and ground plane design for high-current accelerator rails, and stackup and via structure definition.

DensityAI

Package Layout Engineer

FULL_TIME

OTHER

The intern will gain hands-on experience developing automation tools using Cadence Allegro PCB Designer and the SKILL , while supporting high-speed PCB layout projects for networking platforms such as switches and routers. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.

Hewlett Packard Enterprise Company

PCB Layout Automation Intern

equestftpin

Your work will include component placement, controlled-impedance routing, stack-up definition, grounding and shielding strategy, connector and launch design, and isolation of sensitive RF and mixed-signal domains. Preferred Skills and Experience: Experience designing RF and microwave PCB layouts including controlled-impedance routing, launches and transitions, grounding, shielding, and isolation.

Array Labs

Senior RF PCB Layout Engineer

ITAR Requirements: To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. In forging an affordable, accessible, accurate representation of Earth, our work has the potential to transform the face of dozens of fields, including autonomy, telecommunications, disaster relief, gaming, climate science, defense and construction.

Lead RF PCB Layout Engineer

Your work will include component placement, constraint-driven routing, stack-up definition, return path and reference plane strategy, and partitioning between sensitive mixed-signal domains and high-speed digital interfaces. ITAR Requirements: To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State.

Lead High-Speed PCB Layout Engineer

Your work will include component placement, constraint-driven routing, stack-up definition, return path and reference plane strategy, and partitioning between sensitive mixed-signal domains and high-speed digital interfaces. About the Job As a Senior High-Speed PCB Layout Engineer, you will own the physical implementation of Array’s high-speed digital and mixed-signal electronics in Altium, translating schematics and performance requirements into layouts and functional designs.

Senior High-Speed PCB Layout Engineer

Tenstorrent is looking for a Mixed Signal IC Layout Design Engineer role involves full-custom physical layout of analog and mixed-signal integrated circuits, turning schematics into manufacturable layouts that meet performance, power, area, and reliability targets in advanced FinFET processes. An experienced analog/mixed-signal IC layout engineer with strong full-custom layout background on high-speed blocks (PLLs, VCOs, ADCs, DACs, LDOs, comparators, clock generators, high-speed I/Os).

Tenstorrent

Mixed Signal IC Layout Engineer

Tenstorrent Inc

5+ years of experience with Cadence Virtuoso Layout XL tools including cell level design and top-level verification tasks including full-chip DRC, LVS and metal density/slot. Under these laws and regulations, U.S. persons (which includes U.S. citizens, U.S. nationals, lawful permanent residents, refugees, and asylees) working for Keysight can access export-controlled items without authorization from the U.S. government.

Keysight Technologies Inc

Analog/RF IC Layout Design Engineer

The intern will gain hands-on experience developing automation tools using Cadence Allegro PCB Designer and the SKILL, while supporting high-speed PCB layout projects for networking platforms such as switches and routers. Please note that Hewlett Packard Enterprise (HPE), its direct and indirect subsidiaries and affiliated companies, and its authorized recruitment agencies/vendors will never charge a candidate a registration fee, hiring fee, or any other fee in connection with its recruitment and hiring process.

Hewlett Packard Enterprise Co

Our boards need to work across a wide range of constraints: high-speed digital interfaces, low-speed control and sensing circuits, power distribution, mechanical packaging, thermal limits, regulatory requirements, supplier capability, and fast-moving engineering schedules. Our customers include the world's largest and most prominent healthcare systems, governments, retailers, restaurants and global businesses who rely on us to save lives, reduce emissions, increase economic opportunity, and provide delivery from point A to point B as fast as possible.

ZipLine

Electrical PCB Layout Engineer

Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise. Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.

Ursus, Inc.

Senior SRAM Layout Design Engineer

jobdiva

Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

SiTime Corp

Principal Engineer, Layout Design

Your work will include component placement, constraint-driven routing, stack-up definition, return path and reference plane strategy, and partitioning between sensitive mixed-signal domains and high-speed digital interfaces. In forging an affordable, accessible, accurate representation of Earth, our work has the potential to transform the face of dozens of fields, including autonomy, telecommunications, disaster relief, gaming, climate science, defense and construction.

Array Labs Inc

To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State. Your work will include component placement, controlled-impedance routing, stack-up definition, grounding and shielding strategy, connector and launch design, and isolation of sensitive RF and mixed-signal domains.

Dishwasher Jobs in California

Nabet On-Call Brand And Motion Graphics Designer / Designer 2 KQED

Senior Substrate Layout Design engineer - 176158 Zp Group Llc

Senior Substrate Layout Design engineer - 177107 Zp Group Llc

PCB Layout Engineer Lunar Energy

Senior Director, AMS Layout Engineering Upscale AI Inc

Package Layout Engineer DensityAI

PCB Layout Automation Intern Hewlett Packard Enterprise Company

Senior RF PCB Layout Engineer Array Labs

Lead RF PCB Layout Engineer Array Labs

Lead High-Speed PCB Layout Engineer Array Labs

Senior High-Speed PCB Layout Engineer Array Labs

Mixed Signal IC Layout Engineer Tenstorrent

Mixed Signal IC Layout Engineer Tenstorrent Inc

Analog/RF IC Layout Design Engineer Keysight Technologies Inc

PCB Layout Automation Intern Hewlett Packard Enterprise Co

Electrical PCB Layout Engineer ZipLine

Senior SRAM Layout Design Engineer Ursus, Inc.

Principal Engineer, Layout Design SiTime Corp

Senior High-Speed PCB Layout Engineer Array Labs Inc

Senior RF PCB Layout Engineer Array Labs Inc

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