UNKNOWN

FEED

Define the research and measurement models Salesforce needs for human-agent collaboration, including trust, delegation, autonomy, authority, observability, intervention, correction, escalation, learning, and recovery. Recruit and develop an exceptional bench of research leaders, distinguished researchers, behavioral scientists, measurement experts, research technologists, knowledge architects, and Research Operations talent.

YEAR

Salesforce Inc

SVP, Research & Insights - Experience Design

The role bridges internal cross‑functional groups, external customers, and technology providers to deliver optical and advanced packaging solution and roadmap from prove of concept (PoC) to high volume production (HVM). You will be a key contributor in the development of optical‑interconnect packaging and 2.5D/3D/3.5D packaging solutions (CoWoS, SoIC, COUPE, CPO, HBM, FCBGA) that support our AI, Datacenter/HPC product families.

MediaTek Inc

Optical 3D Packaging Technologist

You'll support the SoC design team with subsystem development, third-party IP integration, and PPA (power, performance, area) optimization for Quadric's GPNPU platform - gaining exposure to real front-end design and integration methodologies, and working closely with the architects who define the chip. Quadric is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable architecture.

HOUR

Quadric

RTL Soc Design Intern

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You'll support the Design Verification team in documenting test plans, writing and debugging tests, and generating coverage for Quadric's GPNPU - gaining exposure to real verification methodologies used on CPU and GPU-class designs, and working closely with the architects and designers who built them. Quadric is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable architecture.

Design Verification Intern

The actual base salary offered will depend on a number of factors, including the specific level of the role, years and depth of relevant experience, technical skills and competencies, the criticality of the role to the business, internal equity, and work location. Quadric is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable architecture.

Staff Soc Design Engineer

About Supermicro: Supermicro is a Top Tier provider of advanced server, storage, and networking solutions for Data Center, Cloud Computing, Enterprise IT, Hadoop/ Big Data, Hyperscale, HPC and IoT/Embedded customers worldwide. The candidate will play a key role in the development process of in-house server motherboards, by working collaboratively with cross-functional engineering team as well as outside partners to ensure the robust design of the boards.

Super Micro Computer, Inc. or Supermicro® (NASDAQ: SMCI), a global leader in high-performance, high-efficiency server technology and innovation is a premier provider of end-to-end green computing solutions for Enterprise IT, Datacenter, Cloud Computing, HPC and Embedded Systems worldwide. Supermicro's advanced server Building Block Solutions® offers a vast array of modular, interoperable components for building energy-efficient,pplication-optimized, computing solutions. This broad line of products includes servers, blades, GPU systems, workstations, motherboards, chassis, power supplies, storage technologies, networking solutions and SuperRack® cabinets/accessories. Architecture innovations include Twin Architecture, SuperServer®, SuperBlade®, MicroCloud, Super Storage Bridge Bay (SBB), Double-Sided Storage™, Universal I/O (UIO) and WIO expansion technology all of which deliver unrivaled performance and value.

Super Micro Computer Inc

Hardware Design Engineer

As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. As a Senior Chiplet Physical Design Engineer at Tenstorrent, you will work on a high-profile, cutting-edge program designing and integrating multiple chiplets into a System-in-Package (SiP).

Tenstorrent

Chiplet Physical Design Engineer

As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level.

Top Level Physical Design Engineer

As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2).

Physical Design Engineer

As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. Use Python, Perl, and Tcl for automation and flow development; experience with SPICE, PNR, placement, CTS, routing, post-route optimization, DFT, or AI-based automation is a plus.

Tenstorrent Inc

Physical Design Engineer, Timing

You will develop and maintain AI-enabled design-automation tooling; build automation using Python and EDA-specific scripting languages; partner with CAD on tool and PDK configuration; and help define and support scalable EDA flows that enable faster, more reliable mixed-signal design iteration. Partner with Design Automation and CAD to build workflows, configure tools and PDKs, qualify supported versions, and maintain reproducible environments.

EDA Tools & Design Automation Engineer

As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. I3C, UART), signoff breadth (DRC/LVS, EM/IR, LEC/Formality), multi-clock/CDC-aware implementation, PLL/DLL integration, and DFT-aware physical implementation (OCC/MBIST).

Physical Design Engineer, Pnr

This role combines deep physical design expertise with organization-level technical leadership, enabling predictable RTL-to-GDS execution, strong PPA outcomes, and scalable methodology adoption across multiple projects and teams. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.

Physical Design CPU Methodology Engineer

Essential Duties and Responsibilities: As a Staff Hardware Design Engineer who is responsible for completing assigned projects from development through to end of life, including creating schematics, check layout, component survey, specifications and datasheet study, motherboard and system bring up, bug fix, customer issues analyze, even support colleagues projects. About Supermicro: Supermicro is a Top Tier provider of advanced server, storage, and networking solutions for Data Center, Cloud Computing, Enterprise IT, Hadoop/ Big Data, Hyperscale, HPC and IoT/Embedded customers worldwide.

Staff Hardware Design Engineer

Essential Duties and Responsibilities: Power Architecture & Design: Lead the end-to-end design, schematic capture, and BOM selection for high-current server motherboard DC-DC power delivery systems, including multiphase voltage regulator modules (VRMs), point-of-load (POL) regulators, and power management circuits. PCB Layout & PI Direction: Establish PCB power layer stackup constraints, define high-current routing strategies to minimize parasitic inductance and loop resistance, and collaborate closely with CAD/layout engineers on power integrity (PI) and EMI compliance.

Sr. Hardware Design Engineer

The ideal engineer will not just lead a team, but will be a hands-on, and shall have 5+ years ITE server power supply design experiences, cover PFC, flyback, LLC, phase shift, power sharing, OringFET applications in mass production with records. About Supermicro: Supermicro is a Top Tier provider of advanced server, storage, and networking solutions for Data Center, Cloud Computing, Enterprise IT, Hadoop/ Big Data, Hyperscale, HPC and IoT/Embedded customers worldwide.

Sr. Power Supply Design Engineer

Partner closely with full-chip/chiplet teams to meet all tapeout requirements and with the analog design team to resolve interface issues (LEF/LIB, constraints, integration/debug). As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency.

Physical Design Engineer: Die-To-Die Interface (Rtl To Gdsii)

Tenstorrent is seeking an Physical Design Engineer to lead cross-functional efforts to solve complex physical design challenges and develop end-to-end RTL-to-GDS methodologies across advanced nodes, with a strong focus on PPA and runtime improvements. The engineer will architect, integrate, and deploy AI/ML-driven solutions into production physical design flows, creating custom CAD tools and partnering with internal teams and EDA vendors to drive next-generation, ML-enabled capabilities.

Design Technologist Jobs in San Francisco, CA

SVP, Research & Insights - Experience Design Salesforce Inc

Optical 3D Packaging Technologist MediaTek Inc

RTL Soc Design Intern Quadric

Design Verification Intern Quadric

Staff Soc Design Engineer Quadric

Hardware Design Engineer Super Micro Computer Inc

Chiplet Physical Design Engineer Tenstorrent

Top Level Physical Design Engineer Tenstorrent

Physical Design Engineer Tenstorrent

Physical Design Engineer, Timing Tenstorrent Inc

EDA Tools & Design Automation Engineer Tenstorrent Inc

Physical Design Engineer, Pnr Tenstorrent

Physical Design CPU Methodology Engineer Tenstorrent

Physical Design CPU Methodology Engineer Tenstorrent Inc

Staff Hardware Design Engineer Super Micro Computer Inc

Sr. Hardware Design Engineer Super Micro Computer Inc

Sr. Power Supply Design Engineer Super Micro Computer Inc

Physical Design Engineer: Die-To-Die Interface (Rtl To Gdsii) Tenstorrent

Physical Design Engineer, Timing Tenstorrent

Ai/Ml Physical Design Flow Engineer Tenstorrent

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