Integration RTL Design Engineer Advanced Micro Devices, IncIntegration RTL Design EngineerSan Jose, CaliforniaFull ASIC Development Lifecycle: Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation. RTL Design & Microarchitecture: Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets and timing requirements.
Packaging Design Engineer Advanced Micro Devices, IncPackaging Design EngineerSan Jose, CaliforniaThis role requires good communication skills to work with other teams and engineers at the various design centers to carry the projects from design start to signoff stages. The AECG - Embedded Team builds and optimizes platforms for embedded and commercial applications, working across silicon, firmware, and software to deliver reliable, high‑performance solutions at scale.
RTL Tools & Methodology Engineer Advanced Micro Devices, IncRTL Tools & Methodology EngineerSan Jose, CaliforniaYou are comfortable working on a small, highly capable team where initiative and ownership are valued, and you enjoy collaborating with design and verification teams to continuously improve engineering processes. Collaborate with the design team to drive continuous improvements in front-end design methodologies, ensuring top-quality RTL across areas such as Lint, CDC, formal equivalence, and low-power verification.
SerDes RTL Design Engineer Advanced Micro Devices, IncSerDes RTL Design EngineerSan Jose, CaliforniaAMD SerDes Technology team is searching for a passionate and innovative RTL design engineer to develop high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives.
Systems Application Engineer Advanced Micro Devices, IncSystems Application EngineerSanta Clara, CaliforniaIn this customer-centric role, you will collaborate with external OEM partners, internal development and validation teams, and cross-functional stakeholders to bring next-generation server platforms to market powered by AMD’s Instinct Accelerators—and ensure their successful deployment in customer data centers. Join AMD’s Datacenter GPU Platform Application Engineering team as a System Application Engineer, supporting our Data Center GPU customers across Cloud, HPC, and OEM segments.
EMC Design & Test Engineer (Teradyne, San Jose, CA) Teradyne, Inc.EMC Design & Test Engineer (Teradyne, San Jose, CA)San Jose, CA$122,500–$196,000 / yearInterpret and perform EMC test methods including Radiated Emissions, Conducted Emissions, ESD, Radiated Immunity, EFT/Burst, Surge, Conducted Immunity, Magnetic Field Immunity, Voltage Dips/Interrupts, Harmonics, and Flicker. Bachelor's degree in Electrical or Electronics Engineering or Physics; or equivalent combined experience and education - which would include an associate's degree or technical school certification or related military training in electronics.
Ai/Ml Physical Design Flow Engineer TenstorrentAi/Ml Physical Design Flow EngineerSanta Clara, CATenstorrent is seeking an Physical Design Engineer to lead cross-functional efforts to solve complex physical design challenges and develop end-to-end RTL-to-GDS methodologies across advanced nodes, with a strong focus on PPA and runtime improvements. The engineer will architect, integrate, and deploy AI/ML-driven solutions into production physical design flows, creating custom CAD tools and partnering with internal teams and EDA vendors to drive next-generation, ML-enabled capabilities.
Senior Formal Verification Engineer - AI Soc Development Intel Corp.Senior Formal Verification Engineer - AI Soc DevelopmentSanta Clara, CA$220,920–$311,890 / yearHarnessing the capability of the cloud, the ubiquity of the Internet of Things, the latest advances in memory and programmable solutions, and the promise of always-on 5G connectivity, Intel is disrupting industries and solving global challenges. As a Senior Formal Verification Engineer, you will play a critical role in ensuring the functional correctness of complex digital designs using advanced formal methods.
Lead Android Platform Engineer LogitechLead Android Platform EngineerSan Jose, California$168,000–$240,000 / yearLogitech also offers Wellness Programs, Health Savings Account Plans, access to Expert Medical Opinions, Identity Theft Protection, Breast Milk Delivery to Nursing Mothers on Business Travel, access to a Group Legal Plan, Donations Matching Programs, Employee Product Discounts, and access to Auto, Home, and Pet Insurance. The candidate should also have deep domain knowledge in at least one major Android subsystem such as the Camera Framework, Display Framework, or Audio Framework , with the ability to work across multiple subsystems as needed.
Soc Logic Design Engineer Intel Corp.Soc Logic Design EngineerSanta Clara, CA$141,910–$200,340 / yearBachelor's degree in Electrical Engineering, Computer Engineering, or a related specialized field with 4+ years of hands-on experience in logic design, RTL development, and microarchitecture implementation, or Master's degree with 3+ years of experience in the same fields. This position resides within Intel's leading-edge silicon engineering group, which is dedicated to designing, developing, and scaling advanced semiconductor solutions for a wide range of applications.
Sr. Logic Design Engineer Intel Corp.Sr. Logic Design EngineerSanta Clara, CA$141,910–$200,340 / yearMinimum Qualifications: Candidate must possess a Bachelor's degree in Electrical or Computer Engineering or a related field and 4+ years' experience OR a Master's degree in Electrical or Computer Engineering or a related field and 2+ years' experience OR a PhD in Electrical or Computer Engineering or a related field and 1+ years' experience. Job Details: Job Description: Intel's HIPD team is looking for an experienced senior Logic design engineer to join the rapidly growing UCIE PHY IP for Intel's flagship datacenter/server designs.
Lead Analog Serdes Architect/Design Engineer Intel Corp.Lead Analog Serdes Architect/Design EngineerSanta Clara, CA$220,920–$311,890 / yearThe ideal candidate should have a minimum of MS in Electrical Engineering with 8+ years of experience in high-speed serial links and deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies. Our charter encompasses defining business strategy and roadmaps, product management, developing ecosystems and business opportunities, delivering strong financial performance, and reinvigorating x86 leadership.
Mixed Signal Logic Design Engineer Intel Corp.Mixed Signal Logic Design EngineerSan Jose, CA$122,440–$232,190 / yearApplies various strategies, tools, and methods for mixed signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Job Details: Job Description: Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or highspeed IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Senior Design Verification Engineer Intel CorpSenior Design Verification EngineerSanta Clara, CA$164,470–$311,890 / yearAdditional Locations: Business group: The Central Engineering Group (CEG) is Intel''s data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). Experience in interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; cache coherency and memory consistency models.
Principal Engineer, AMS IP Architecture Intel CorpPrincipal Engineer, AMS IP ArchitectureSanta Clara, CA$220,920–$311,890 / yearD. in Electrical Engineering, Computer Engineering, or a related field with focus on high-speed communications, analog circuits, or signal processing • Deep expertise in one or more of the following: SerDes modeling in MATLAB or Simulink, high-speed analog CMOS design, DSP techniques for SerDes equalization and timing recovery, or communications theory including equalization, coding, and noise filtering • Experience analyzing and closing link budgets for NRZ or PAM4 signaling at 100Gbps or higher, accounting for transmitter impairments, channel loss, reflection, crosstalk, and receiver noise • Hands-on work with SerDes transmitter and receiver architectures, equalization techniques such as FFE, DFE, and CTLE, or CDR loop dynamics and jitter tolerance • Ability to correlate models with silicon measurements, debug discrepancies systematically, and update models to reflect real-world behavior • Familiarity with C, Verilog-A, or SystemVerilog for co-simulation or algorithm prototyping is a plus. Business group: The Central Engineering Group (CEG) is Intel''s data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies).
Sr. Staff ASIC Verification Engineer Recogni IncSr. Staff ASIC Verification EngineerSunnyvale, CAResponsibilities: Your responsibilities will be wide-ranging and and run the gamut of working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular SystemVerilog and UVM, handling bug tracking and coverage convergence and developing scripts and methodologies for the front-end ASIC flow. This ASIC's design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to deliver the high-performance multi-chip silicon solutions that are at the heart of Tensordyne's vertically integrated, generative AI inference acceleration systems for data centers.
Hardware Infrastructure & CI/CD Engineer EfficientAI CorpHardware Infrastructure & CI/CD EngineerSan Jose, CA$180,000–$220,000 / yearThe ideal candidate must be a full-stack infrastructure engineer who is equally comfortable writing Go services, managing Kubernetes environments, debugging low-level test programs, and working with a wide variety of embedded hardware such as FPGA, Ambiq, Apollo, PIC32 and Efficient E1. ATLAS supports automated benchmarking and validation of both our company''s products and competitor hardware, providing essential data that drives engineering and product decisions.
EMC Design & Test Engineer (TERADYNE, San Jose, CA) Teradyne IncEMC Design & Test Engineer (TERADYNE, San Jose, CA)San Jose, CA$122,500–$196,000 / yearInterpret and perform EMC test methods including Radiated Emissions, Conducted Emissions, ESD, Radiated Immunity, EFT/Burst, Surge, Conducted Immunity, Magnetic Field Immunity, Voltage Dips/Interrupts, Harmonics, and Flicker. Bachelor's degree in Electrical or Electronics Engineering or Physics; or equivalent combined experience and education - which would include an associate's degree or technical school certification or related military training in electronics.
Performance Library Engineer EfficientAI CorpPerformance Library EngineerSan Jose, CA$130,000–$230,000 / yearIn this role, you will take ownership of complex, performance-critical, library development while working closely with Efficient's compiler and embedded teams providing direct feedback on compiler enhancements and performance related tools. Efficient's Performance Library Engineers create and optimize libraries and frameworks that are used by customers of the world's most energy-efficient programmable processor (the "Fabric").
Performance Research Engineer multiple levels EfficientAI CorpPerformance Research Engineer multiple levelsSan Jose, CA$180,000–$250,000 / yearEfficient's Performance Research Engineers research new optimization techniques; design new tools for AI assisted optimization and performance analysis; collaborate with our architecture team on the design of future hardware; design and perform modeling experiments using our architecture simulator; and collaborate with our world class compiler team, evaluating code-generation quality, suggesting new intrinsics, influencing the ISA, and experimenting with new language extensions. Excellent written, verbal, analytical and technical communication skills, with the ability to clearly document complex systems, lead discussions across teams, as well as the ability to drive consensus across teams.
RTL Design Engineer Advanced Micro Devices IncRTL Design EngineerSan Jose, CAKEY RESPONSIBILITIES: RTL Design & Microarchitecture: Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets and timing requirements. Full ASIC Development Lifecycle: Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation.
Sr. ASIC Verification Engineer Recogni IncSr. ASIC Verification EngineerSunnyvale, CAResponsibilities: Your responsibilities will be wide-ranging and and run the gamut of working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks, developing comprehensive test and coverage strategies, implementing the verification environment and tests using object-oriented tools, in particular SystemVerilog and UVM, handling bug tracking and coverage convergence and developing scripts and methodologies for the front-end ASIC flow. This ASIC's design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to deliver the high-performance multi-chip silicon solutions that are at the heart of Tensordyne's vertically integrated, generative AI inference acceleration systems for data centers.
Senior RTL Design Engineer Advanced Micro Devices IncSenior RTL Design EngineerSan Jose, CAKEY RESPONSIBILITIES: RTL Design & Microarchitecture: Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets and timing requirements. Full ASIC Development Lifecycle: Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation.
Principal Product Engineer Cadence Design Systems IncPrincipal Product EngineerSan Jose, CA$136,500–$253,500 / yearJob responsibilities: Perform Product Engineering work for Genus Synthesis Solution (Genus), a logic synthesis software used for synthesizing a design described in a high-level language into logic gates, to achieve best-in-class Power, Performance & Area (PPA) for latest digital ASICs. Experience in Logic Design and Synthesis, Formal Verification, Low Power design, Physical Design and Timing Closure for block level and top level designs.
Systems Application Engineer- (Mandarin) Advanced Micro Devices IncSystems Application Engineer- (Mandarin)Santa Clara, CAIn this customer-centric role, you will collaborate with external OEM partners, internal development and validation teams, and cross-functional stakeholders to bring next-generation server platforms to market powered by AMD's Instinct Accelerators-and ensure their successful deployment in customer data centers. THE ROLE: Join AMD's Datacenter GPU Platform Application Engineering team as a System Application Engineer, supporting our Data Center GPU customers across Cloud, HPC, and OEM segments.
System Software Engineer, Networking Recogni IncSystem Software Engineer, NetworkingSunnyvale, CADrive route, neighbor, next-hop, and ECMP programming flows from control-plane intent all the way to confirmed ASIC hardware state, and build mechanisms that distinguish control-plane acceptance from SDK acceptance from hardware programming acknowledgement. This is a deeply technical, hands-on role for someone who is at home moving up and down the stack - tuning userspace services, patching kernel drivers, and reaching into firmware - to squeeze latency, bandwidth, and reliability out of large, lossless networks.
Field Application Engineer MKIS Professional SearchField Application EngineerSanta Clara, CaliforniaOur client is a global leader in low-power, short-range wireless connectivity semiconductor solutions , consistently ranked as a top vendor in the BLE (Bluetooth Low Energy) space. With a strong portfolio of customer design wins and a robust product roadmap, we are helping to expand the technical support team to accelerate growth across key markets.
Applications Engineer EfficientAI CorpApplications EngineerSan Jose, CA$160,000–$210,000 / yearIf you thrive on solving technical challenges, enjoy working hands-on with both hardware and software, and love collaborating directly with customers to bring solutions to life, this is the role for you. In this role, you will design and implement embedded computing solutions tailored to customer use cases, enabling them to fully leverage the power of Efficient's architecture.
AI/ML Physical Design Flow Engineer Tenstorrent IncAI/ML Physical Design Flow EngineerSanta Clara, CATenstorrent is seeking an Physical Design Engineer to lead cross-functional efforts to solve complex physical design challenges and develop end-to-end RTL-to-GDS methodologies across advanced nodes, with a strong focus on PPA and runtime improvements. The engineer will architect, integrate, and deploy AI/ML-driven solutions into production physical design flows, creating custom CAD tools and partnering with internal teams and EDA vendors to drive next-generation, ML-enabled capabilities.
Staff Equipment Engineer, Controls BloomEnergyStaff Equipment Engineer, ControlsFremont, CA$114,800–$165,200Our cutting-edge solutions enable unparalleled “time-to-power” capabilities, reliability, and sustainability, ensuring our customers remain ahead in a world where soaring energy demand and intensifying energy scarcity are rapidly becoming the new norm. Functional knowledge of PLC’s, low voltage controls, three phase power distribution, industrial control panels, electronic sensors, pneumatics and hydraulics .
Mechatronics Test Engineer, Drive Systems Tesla IncMechatronics Test Engineer, Drive SystemsPalo Alto, CA$91,600–$195,600 / yearThe Drive Systems Engineering Test team at Tesla works with the drive unit design team to facilitate development of the drive unit components and subsystems such as motors, gears, and pumps. Design mechanical and electrical hardware for test equipment which facilitates the development of drive unit components (stators, rotors, gears, bearings, pumps, and structures).
Integration Engineer, Keys & Authentication Tesla IncIntegration Engineer, Keys & AuthenticationPalo Alto, CA$140,000–$300,000 / yearThis role will involve evaluating future technologies as well as ensuring current production systems work flawlessly, by collaborating with various cross-functional teams, including design (software, electrical and mechanical), validation, manufacturing, service, and program management. This role will work with various wireless technologies (BLE, UWB, NFC) in combination with iOS, Android, and other custom devices, as well as optimize systems in the context of many vehicle platforms and connected backend services.
Controls Engineer, Megapack Site Controls Tesla IncControls Engineer, Megapack Site ControlsPalo Alto, CA$120,000–$252,000 / yearOur team designs control systems integrating Megapacks with energy generation, such as solar, wind and gensets, into applications such as power plants, data centers and microgrids. Ability to communicate findings in a concise & clear manner and ability to work cross functionally with engineering, business development, and deployment personnel.
Internship, Reliability Test Engineer, Energy Engineering (Fall 2026) Tesla IncInternship, Reliability Test Engineer, Energy Engineering (Fall 2026)Palo Alto, CA$20–$50 / hourWork closely with internal and external teams (design, firmware, manufacturing, service, etc.) to execute engineering validation and long-term reliability testing programs at critical component and system-levels. The Energy Products Reliability team is a diverse, multi-disciplinary group of engineers focused on delivering the most reliable, robust and capable energy, solar and charging products.
Sr. System Integration Engineer, Residential Ecosystem Tesla IncSr. System Integration Engineer, Residential EcosystemPalo Alto, CA$140,000–$252,000 / yearTo ensure Teslas overall mission of accelerating the worlds transition to sustainable energy, the Tesla Energy team is bringing our world-leading battery technology to the grid. Tesla is leveraging its breakthrough firmware, electronics, test, and manufacturing capability to develop and deploy grid-connected storage at residential, industrial, and utility levels.
Sr. Staff Clock Architecture Engineer, AI Hardware Tesla IncSr. Staff Clock Architecture Engineer, AI HardwarePalo Alto, CA$128,000–$432,000 / yearBy creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. Staff Clock Architecture Engineer, you will own the complete clock strategy for the chip - from PLL selection and reference clock planning through topology, jitter budgeting, and RTL integration.
Sr. System Performance Engineer, Residential Charging Products Tesla IncSr. System Performance Engineer, Residential Charging ProductsPalo Alto, CA$120,000–$288,000 / yearExperience with reliability engineering methodologies (FMEA, DFMEA, FTA) and statistical analysis of fleet data to identify failure modes, evaluate product reliability, and drive improvements in charging products or vehicles. Tesla Energy is accelerating the world's transition to sustainable energy through a rapidly growing fleet of residential solar, battery energy storage systems (BESS), and charging systems deployed across hundreds of thousands of homes globally.
System Integration Engineer, Solar Products Tesla IncSystem Integration Engineer, Solar ProductsPalo Alto, CA$120,000–$252,000 / yearTesla is leveraging its breakthrough firmware, electronics, test, and manufacturing capability to develop and deploy grid connected storage at residential, industrial, and utility levels. Own the end-to-end hardware and firmware integration and validation of Tesla's solar energy products, including PV inverters, solar panels, and PV system MPPT and safety functionalities.
Sr. Electronic Design Engineer Tesla IncSr. Electronic Design EngineerPalo Alto, CA$152,000–$348,000 / yearThe ideal candidate will demonstrate a strong understanding of microcontroller design and wireless systems, coupled with expertise in developing next-generation vehicle wireless platforms, including 5G cellular, WiFi, Bluetooth (BT), and GNSS technologies. Along with competitive pay, as a full-time Tesla employee, you are eligible for the following benefits at day 1 of hire: Medical plans > plan options with $0 payroll deduction.
Systems Engineer, Residential Energy Storage Products Tesla IncSystems Engineer, Residential Energy Storage ProductsPalo Alto, CA$100,000–$180,000 / yearExperience with reliability engineering methodologies (FMEA, DFMEA, FTA) and statistical analysis of fleet/field data to identify failure modes, evaluate product reliability, and drive improvements in battery systems or power electronics. Tesla Energy is accelerating the world's transition to sustainable energy through a rapidly growing fleet of residential solar, battery energy storage systems (BESS), and charging systems deployed across hundreds of thousands of homes globally.
BMS Controls Engineer, Infrastructure Tesla IncBMS Controls Engineer, InfrastructurePalo Alto, CA$91,600–$195,600 / yearTroubleshoot hardware, software, and network issues that result in poor data quality (e.g., fixing loose terminations, replacing faulty sensors, or resolving network IP conflicts). You will work closely with facilities personnel to instrument systems, validate sensor accuracy, and architect the data pipeline required to feed predictive Machine Learning models.
Internship, Software Validation Engineer, Vehicle Firmware (Fall 2026) Tesla IncInternship, Software Validation Engineer, Vehicle Firmware (Fall 2026)Palo Alto, CA$42.07–$58.89 / hourThe team is looking for highly motivated interns to support Drive Systems, Brakes, Steering, Suspension, Crash Safety, Thermal Management, HVAC, Body Controls, Lighting, Access Controls, Battery Management, Charging, Power Conversion, High and Low Voltage Power Distribution, Autonomy and Core Test Infrastructure. Consider before submitting an application: This position is expected to start August or September 2026 and continue through fall term (ending approximately December 2026) or continuing into Winter/Spring 2027 if available and there is an opportunity to do so.
Cybersecurity Applications Engineer Tesla IncCybersecurity Applications EngineerPalo Alto, CA$160,000–$330,000 / yearDesign, build, and validate cybersecurity tooling and features - including intrusion detection/prevention systems (IDS/IPS), network monitoring tools, security dashboards, and automation for vulnerability scanning, log analysis, and continuous security monitoring. Security is a crucial part of Tesla's strategy, and we are looking for an exemplary engineer who is passionate about cybersecurity, stays up to date with technological changes in both cybersecurity threats and tools, willing to challenge and improve existing industry best practices.
Hardware Design Engineer Recogni IncHardware Design EngineerSunnyvale, CAYou will be in a unique position to have ownership of a wide-ranging list of hardware system development aspects, including schematics, PCB layout and mechanical design, component selection and collaborating with operations in AVL management, EVT/DVT/PVT testing and certification. Our mission, through the creation of custom silicon, hardware and software, is to enable multimodal Generative AI inference acceleration at scale, with safe, sustainable, high-performance systems for our hyperscaler and neocloud data center customers.
Senior Research Engineer, Computer Vision (LFV/WFM) Toyota Research InstituteSenior Research Engineer, Computer Vision (LFV/WFM)Los Altos, CA$180,000–$258,750 / yearAs a Research Engineer, you will be responsible for supporting and optimizing large-scale distributed training of diffusion and transformer models; maintaining the infrastructure that ingests, unifies, and serves heterogeneous multi-modal datasets at scale; and developing tools and pipelines that accelerate the research-to-results cycle. This role requires close collaboration with multiple TRI divisions (Robotics, Automated Driving, Human-Interactive Driving, etc.) as well external Toyota and University partners, and the ability to reconcile and prioritize possibly competing requirements in a fast-paced combination of research and production environments.
Imaging Algorithms & Firmware Engineer indie Semiconductor Inc.Imaging Algorithms & Firmware EngineerSan Jose, CAThe Imaging Engineer will be a key member of indie's Vision Business Unit, working within the Image Signal Processing (ISP) team, which consistently delivers best-in-class automotive image quality powered by indie's high-performance current and next-generation ICs. Degree in Electrical/Electronics Engineering, Computer Engineering/Science, Mechanical/Mechatronics, or Imaging Science, with emphasis on signal/image processing or control systems.
Senior Laser Project Engineer Lawrence Livermore National LaboratorySenior Laser Project EngineerLivermore, CA$175,530–$267,060 / yearPerform offline assembly of laser components; measure, characterize, and analyze performance using laser diagnostics; design and build experimental tests to validate optical amplifiers, polarization components, mirrors, lenses, laser assemblies, and related hardware while supporting quality assurance, troubleshooting, and system performance improvement. Operate under consultative direction with substantial authority, using in-depth analysis and subject matter expertise in highly advanced concepts to resolve a range of highly complex problems, independently determine strategies, modify approaches, and pursue actions that impact organizational operations or directions and achieve long-term goals.
Principal Product Engineer, Synthesis CadencePrincipal Product Engineer, SynthesisSan Jose, CA$136,500–$253,500 / yearJob responsibilities: Perform Product Engineering work for Genus Synthesis Solution (Genus), a logic synthesis software used for synthesizing a design described in a high-level language into logic gates, to achieve best-in-class Power, Performance & Area (PPA) for latest digital ASICs. Experience in Logic Design and Synthesis, Formal Verification, Low Power design, Physical Design and Timing Closure for block level and top level designs.
Sr Hardware Engineer DexCom IncSr Hardware EngineerMesa, AZ$116,600–$194,400 / yearWe drive improvements in throughput and quality while supporting new product and material introductions, ensuring reliable, scalable operations that directly impact business performance and patient outcomes. You have technical expertise in PLC-based automation and machine vision systems, including, troubleshooting, optimization, and lifecycle support of Allen-Bradley/Rockwell controls and Cognex or equivalent vision platforms in a manufacturing environment.
Oracle Cloud Infrastructure (OCI) Security Engineer ICONMA, LLCOracle Cloud Infrastructure (OCI) Security EngineerPhoenix, AZ$46.43 / hourInvestigate, troubleshoot, and resolve OCI and Oracle PaaS technical issues while identifying root causes and implementing long-term solutions. Secure Oracle PaaS environments through appropriate network security, workload isolation, policy enforcement, and data protection controls.