UNKNOWN

FEED

Threat Prevention & Hardening: Implement Microsoft Defender for Endpoint, Defender for Office 365, Defender for Identity, Defender for Cloud Apps, and Defender for Cloud to protect endpoints, email, identities, SaaS apps, and multi-cloud workloads, including attack surface reduction, exploit and network protection, and phishing defenses. Security Operations: Deploy Microsoft Defender XDR and Microsoft Sentinel as a unified SIEM and XDR platform in the Microsoft Defender portal, including transitioning existing Sentinel environments from the Azure portal; build cross-domain detections, automated response, and threat hunting enriched by Microsoft Threat Intelligence; and use Microsoft Security Copilot agents to accelerate triage, investigation, and response.

YEAR

Invoke, LLC

Cloud Solution Architect – Security

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The Senior AI Product Architect will ensure that technical decisions support Anomali's five-level maturity model, enabling customers to progress from intelligence-enriched security operations through increasingly advanced levels of data unification, correlation, decisioning, automation, and agentic security operations. This role will help advance Anomali's architecture thesis around the Intelligent Unification Layer, including the Governed Decisioning Layer, which provides the trusted data, context, governance, auditability, and control required for AI-driven security operations.

Anomali Inc

Senior AI Product Architect (US Remote)

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The JSE Lead Open Systems Architect defines and maintains FSI Defenses open systems architecture strategy for all JSE/SCARS pursuits, ensuring that simulator designs, integration approaches, and product roadmaps align with the MOSA ecosystem and the Governments GRA-based acquisition framework. The role reviews solicitations, Requests for Proposals, and DIU Commercial Solutions Opening (CSO) submissions for open architecture requirements and ensures FSI Defenses technical volumes accurately and compellingly represent the companys GRA alignment.

Aviation professionals from around the world trust FlightSafety International to provide the highest quality training and outstanding service. Our professional instructors deliver aircraft- and mission-specific courses, using our comprehensive training systems and advanced- technology flight simulators designed to enhance safety. Trust your training to FlightSafety.

FlightSafety International Inc

JSE Lead Open Systems Architect

FULL_TIME

The Senior AI Product Architect will ensure that technical decisions support Anomali’s five-level maturity model, enabling customers to progress from intelligence-enriched security operations through increasingly advanced levels of data unification, correlation, decisioning, automation, and agentic security operations. This role will help advance Anomali’s architecture thesis around the Intelligent Unification Layer, including the Governed Decisioning Layer, which provides the trusted data, context, governance, auditability, and control required for AI-driven security operations.

Anomali

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The ideal candidate will bring extensive Salesforce architecture experience, strong client-facing consulting skills, and deep expertise across multiple Salesforce clouds, enterprise integrations, authentication patterns, data migration, and application lifecycle management. Design and develop custom solutions using Apex, triggers, controllers, web services, Lightning Web Components (LWC), and other applicable Salesforce technologies.

HOUR

Diverse Lynx, LLC

SFDC Architect

The Enterprise Architect is expected to bring deep expertise in one or more of these areas while collaborating with Domain, Platform, Solution, and Technical Architects across infrastructure, cloud, data, integration, and cybersecurity to drive enterprise-level decisions and actionable outcomes. Collaborate with Solution Architects, Technical Architects, engineering, infrastructure, security, data, and AI teams to resolve cross-domain architecture challenges and move decisions into execution.

Constantly growing in response to the needs of our customers in all sectors and verticals, SHI has transformed itself from a $1 million "software-only" regional reseller into a $8.5 billion global provider of information technology products and services. Dynamic, scalable, innovative solutions delivered with world-class customer support have made SHI the complete IT hardware, software and professional services solution provider it is today.
Under the guidance of our current ownership for nearly 30 years, SHI has never been faced with a merger or acquisition that could distract us from supporting our customers. Remaining focused on the job at hand has allowed us to forge long-term relationships with the clients and OEM partners who remain our most loyal and ardent supporters. The most important metric by which success can be measured - the rate at which we retain our customers - is 99%, ranking SHI among the highest in our industry or any other!

SHI International Corp

Enterprise Architect

ADAPTED_NOW

The JSE Lead Open Systems Architect defines and maintains FSI Defense's open systems architecture strategy for all JSE/SCARS pursuits, ensuring that simulator designs, integration approaches, and product roadmaps align with the MOSA ecosystem and the Government's GRA-based acquisition framework. This includes decoupling operator interfaces from aircraft-specific implementations, enabling Virtual Aircraft Services (VAS) and reconfigurable cockpit architectures, and integrating simulation components with the JSE Technical Baseline (JTB) via the Global Reusable Interface Domain (GRID).

FlightSafety International

JSE Lead Open Systems Architect (Fort Worth, TX, US, 76155)

Invoke

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The ideal candidate combines deep technical expertise in distributed systems with strong experience in messaging frameworks, integration patterns, and cloud-native architectures, and can translate business requirements into robust, scalable system designs. This role will define architectural patterns for distributed computing, event-driven systems, and enterprise integration, ensuring scalability, resilience, and interoperability across a complex ecosystem of internal and external systems.

Blue Yonder

Distributed Systems Integration Architect ( Leadership Role) - ( US Citizen)

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Work with infrastructure, platform, and cybersecurity teams to define solution requirements and designs for cloud and on-premises environments, including connectivity, identity and access management, secrets management, availability, performance, disaster recovery, and operating cost. Ability to translate complex business processes and requirements into practical solution architectures, lead across multidisciplinary teams without direct supervisory responsibility, and clearly explain technical decisions and trade-offs to senior leaders.

S &amp; B Engineers and Constructors, Ltd. is a privately owned, fully integrated engineering, procurement and construction company that services a diverse set of industries.
S &amp; B was founded on the principles of honesty, integrity and safety. For the last 50 years, S &amp; B has serviced clients in the refining, petrochemical and chemical, midstream, power, infrastructure and pulp and paper industries. As a company with over 4,500 employees, our resources and experience allow us to execute any size project with complete client satisfaction. We also offer our clients flexibility with our resources in order to execute their project in a manner that will ensure success and safety.

S&B Engineers and Constructors

Solution Architect in Memorial Office (West), Texas | Careers at S&B Houston

S & B Engineers and Constructors, Ltd

Work at Home Requirements: To ensure Home or Hybrid Home/Office employees' ability to work effectively, the self-provided internet service of Home or Hybrid Home/Office employees must meet the following criteria: At minimum, a download speed of 25 Mbps and an upload speed of 10 Mbps is required; wireless, wired cable or DSL connection is suggested. In this role, you will partner with EIP and business leaders to assess emerging threats, identify architectural gaps, and design forward-looking security solutions that strengthen Humana''s overall security posture.

Humana Inc

Lead Security Architect

Required Skills & Qualifications: Define enterprise cybersecurity architecture and security patterns for cloud, platform, and data environments. Strong architecture capability across cybersecurity, threat modeling, cloud security, IAM, and data protection.

Cyber Architect

AWS Architecture & Strategy - Enterprise architecture for event-driven pipelines (Lambda, Step Functions, Event Bridge, Kinesis, MSK), AI/ML (Bedrock, SageMaker), multi-database (RDS, Aurora, DynamoDB, Redshift, Fabric). Cloud-Native Data Lake & Market Data Architecture - Delivered unified data lakes ingesting commodity feeds (ICE/CME), ISO pricing/LMPs, forward curves (ZEMA/Morningstar/Platts), historians, and ETRM.

Vistra Corp

Principal Architect, BU

Note that Guidehouse will never charge a fee or require a money transfer at any stage of the recruitment process and does not collect fees from educational institutions for participation in a recruitment event. All communication regarding recruitment for a Guidehouse position will be sent from Guidehouse email domains including @guidehouse.com or guidehouse@myworkday.com.

Guidehouse Inc

Associate Director, Lead Data Architect - Databricks

Albany, NY; Albuquerque, NM; Ashburn, VA; Atlanta, GA; Austin, TX; Baltimore, MD; Baton Rouge, LA; Bentonville, AR; Birmingham, AL; Boise, ID; Boston, MA; Boulder, CO; Buffalo, NY; Charlotte, NC; Chicago, IL; Cincinnati, OH; Cleveland, OH; Columbus, OH; Dallas, TX; Denver, CO; Des Moines, IA; Detroit, MI; El Segundo, CA; Fort Worth, TX; Ft Lauderdale, FL; Greenville, SC; Harrisburg, PA; Hartford, CT; Houston, TX; Indianapolis, IN; Irvine, CA; Jackson, MS; Jacksonville, FL; Kansas City, MO; Knoxville, TN; Las Vegas, NV; Lincoln, NE; Los Angeles, CA; Louisville, KY; McLean, VA; Melville, NY; Memphis, TN; Miami, FL; Milwaukee, WI; Minneapolis, MN; Montvale, NJ; Morristown, NJ; Nashville, TN; New Orleans, LA; New York, NY; Oklahoma City, OK; Omaha, NE; Orlando, FL; Philadelphia, PA; Phoenix, AZ; Pittsburgh, PA; Portland, OR; Providence, RI; Raleigh, NC; Richmond, VA; Rochester, NY; Sacramento, CA; Salt Lake City, UT; San Antonio, TX; San Diego, CA; San Francisco, CA; Santa Clara, CA; Seattle, WA; Shreveport, LA; St Louis, MO; Stamford, CT; Tallahassee, FL; Tampa, FL; Tempe, AZ; Virginia Beach, VA; Washington, DC; Winston-Salem, NC. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness, and safeguard business operations and company reputation.

KPMG International Cooperative

Manager, Solutions Architect

Other Responsibilities: Collaborate with cross-functional teams (Architecture, RTL Design, Verification, DFT, Physical Design, Firmware/Software, Systems, Quality, and Product/Customer teams) to align security, safety, test, and product requirements and to support customer discussions, audits, and security reviews. Job Responsibilities: Define SoC hardware security architecture and requirements, including HSM specification, secure boot/RoT concepts, and cryptographic IP integration strategies.(AES/SHA/PKA/PUF/PQC etc).

NXP Semiconductor, Inc.

Hardware Security Architect

Support post-silicon bring-up of the I/O subsystemBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of relevant industry experience architecting I/O and system subsystems and their hardware/software interfaces - register and programming models, DMA and descriptor interfaces, doorbells, and offload interfaces - for NIC/DPU or comparable ASICs Experience with PCIe data link and transport protocols, including TLP formats, transaction types (posted/non-posted/completions), and ordering rules Experience with I/O virtualization technologies such as SR-IOV and SIOV Experience with PCIe capabilities such as Advanced Error Reporting, Downstream Port Containment, and Integrity and Data Encryption Experience with on-chip scheduling and arbitration architectures and quality-of-service mechanisms - transaction/packet schedulers, arbiters, traffic shapers, and rate limiters (meters/policers, token buckets) - and their impact on latency, fairness, bandwidth partitioning, and throughput Experience with symmetric and asymmetric cryptography concepts and inline data encryption (e.g., AES-XTS, AES-GCM) Experience with x86 and/or ARM system architecture, including virtualization technologies, IOMMUs, and interrupt virtualization Experience with data center workloads and their I/O characteristics Experience driving architectural decisions independently and influencing their direction through data PhD in Computer Science, Computer Engineering or Electrical Engineering 15+ years of relevant industry experience architecting I/O and system subsystems and hardware/software interfaces for NIC/DPU or comparable ASICs Experience designing PCIe endpoints and root complexes Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysis Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs Experience with system-management concepts including server/BMC interactions, and protocols such as I2C, I3C, USB/Ethernet, USB/MCTP, and SPI/eSPI Experience designing high-performance DMA engines and offload accelerators, such as for cryptography and compression Experience with post-silicon performance validation and model-to-hardware correlation methodologies Understanding of Confidential Computing use cases and the related PCIe protocols -- Data Object Exchange (DOE), Security Protocol and Data Model (SPDM), Management Component Transport Protocol (MCTP), and TEE Device Interface Security Protocol (TDISP)Meta builds technologies that help people connect, find communities, and grow businesses. Own the I/O subsystem architecture for our DPUs - PCIe, DMA and offload engines, I/O virtualization, confidential computing, and system management -- from early path-finding through silicon bring-up Decide what runs in hardware, what runs in firmware, and what stays in host software, and design the interfaces between them Define the hardware/software interface - register and programming models, descriptor and doorbell interfaces, error and interrupt models, and the offload interfaces firmware and drivers build on Work closely with firmware, driver, and software teams so the interface is clean, efficient, and genuinely usable, and evolve it as their needs change Weigh the performance, power, and area trade-offs behind your choices and back them with data, partnering with performance modeling where deeper analysis is needed Work closely with design, DV, and PD teams on feature definition and PPA tradeoff; refine architecture to meet the design and PD constraints.

Meta Platforms Inc

DPU IO Architect, Infrastructure Silicon

Support post-silicon bring-up of the Networking functionalityBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of relevant industry experience architecting Networking datapaths and packet-processing pipelines and their hardware/software interfaces for NIC/DPU or comparable ASICs Experience with SmartNIC/IPU/DPU architectures and their usages: Network virtualization, storage disaggregation, overlay networking, virtual switch, firewall/ACLs, and PSP gateways, including offload mechanisms Experience with datacenter Networking technologies and protocols such as Ethernet, IPv6, TCP/UDP, Geneve, PSP, and SRv6, including offload mechanisms for TCP segmentation, reassembly, checksum, and receive-side scaling Experience with RDMA and storage protocols and fabrics, including RoCEv2 and NVMe/NVMe-over-Fabric (TCP and RDMA) Experience with congestion control (e.g., DCQCN) and emerging transports such as UET and comparable next-generation RDMA transports Experience with on-chip scheduling and arbitration architectures and quality-of-service mechanisms -- transaction/packet schedulers, arbiters, traffic shapers, and rate limiters (meters/policers, token buckets) -- and their impact on latency, fairness, bandwidth partitioning, and throughput Experience with datacenter network topologies and fabric architectures (e.g., Clos/fat-tree, rail-optimized fabrics) and their performance implications, including oversubscription, ECMP/load balancing, and end-to-end latency and congestion behavior Experience with symmetric and asymmetric cryptography concepts and inline data encryption (e.g., IPSec, PSP) Experience with domain-specific dataplane languages such as P4 Experience with data center workloads and their networking characteristics Experience with analytical performance-modeling methods (e.g., queueing theory, Little's Law, bandwidth-delay/outstanding-transaction sizing) Experience driving analysis independently and influencing architectural direction through data PhD in Computer Science, Computer Engineering or Electrical Engineering 15+ years of relevant industry experience architecting networking datapaths and packet-processing pipelines and their hardware/software interfaces for NIC/DPU or comparable ASICs Experience designing high-performance offload architectures for NVMe-over-Fabric Experience designing data-plane offload/acceleration architectures using programmable processors/engines (programmable parsers, match-action, etc.) Experience designing high-performance inline data encryption engines, such as for IPSec and PSP Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows Experience with GPU, machine learning, multi-threaded programming paradigm Experience with emerging RDMA transports such as UET and comparable next-generation RDMA protocols Experience with post-silicon performance validation and model-to-hardware correlation methodologies Experience with performance modeling and workload characterization for networking architectures, including analytical methods (e.g., queueing theory, Little's Law) and frameworks such as SystemC Experience with high-level synthesis, power-performance-area trade-off analysis, or PPA-driven microarchitectural optimization Experience designing scheduling, arbitration, or rate-limiting/traffic-management hardware (e.g., hierarchical schedulers, WRR/DWRR/strict-priority arbiters, shapers/policers) Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysisMeta builds technologies that help people connect, find communities, and grow businesses. Architect the Networking datapath for our DPUs - packet processing and offloads, Network virtualization and overlays, RDMA and storage transports, and inline security - from early path-finding through silicon bring-up Decide what runs in the datapath engines, what runs in firmware, and what stays in host software, and design the interfaces between them Define how software programs and controls the datapath - match-action tables, rule and flow programming, register and descriptor interfaces, and the offload interfaces firmware and drivers build on Work closely with firmware, driver, and software teams so the datapath and its interfaces are clean, efficient, and genuinely usable, and evolve them as needs change Work closely with design, DV, and PD teams on feature definition and PPA tradeoff; refine architecture to meet the design and PD constraints.

DPU Networking Architect, Infrastructure Silicon

Analyze performance of current and future SmartNIC/IPU/DPU architectures with focus on end-to-end transaction flows, host-to-DPU offloading options, evaluation of SoC architectural options Quantify architectural/micro-architectural trade-offs wrt PPA to inform and guide design decisions Analyze and characterize DPU workloads to abstract key performance-relevant behaviors and incorporate into representative models and synthetic benchmarks Develop and enhance performance models, simulation tools, and methodologies to evaluate future DPU architectures Drive RTL performance validation, including development of comprehensive performance test plans, coverage criteria, and correlation of RTL results against architectural models Correlate pre-silicon performance projections with post-silicon measurements and drive methodology improvements based on findingsBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of relevant industry experience in developing analytical/tool based models and performance analysis with focus on networking and storage architectures Detailed understanding of DPU architectures: network virtualization, storage disaggregation, networking and storage protocols such as RoCE, NVMe, fabric architectures Experience in workload analysis and characterization, and abstracting key performance features into models for analysis Proficiency in languages for model development (e.g. Python, C/C++, SystemC) Experience with data center workloads and benchmarking methodologies Experience with RTL performance validation, including authoring and executing performance test plans and correlating pre-silicon performance models with post-silicon measurements Experience driving analysis independently and influencing architectural direction through data PhD in Computer Science, Computer Engineering or Electrical Engineering 15+ years of relevant industry experience in developing analytical/tool based models and performance analysis with focus on networking and storage architectures Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs Experience with post-silicon performance validation and model-to-hardware correlation methodologies Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysis Experience with GPU, machine learning, multi-threaded programming paradigm Experience with high-level synthesis, power-performance-area trade-off analysis, or PPA-driven microarchitectural optimizationMeta builds technologies that help people connect, find communities, and grow businesses.

DPU Performance Architect, Infrastructure Silicon

Cloud Data Platform Leadership Lead the design and implementation of cloud-based data platforms using technologies such as Snowflake, Prefect, Google Cloud Platform (Eligible to workP), Azure and Databricks Define best practices for data storage, processing, orchestration, and security. The Data Architect responsible for developing blueprints for all data repositories, evaluating hardware and software platforms, and integrating systems.

Architect Jobs in Texas

Cloud Solution Architect – Security Invoke, LLC

Senior AI Product Architect (US Remote) Anomali Inc

JSE Lead Open Systems Architect FlightSafety International Inc

Senior AI Product Architect (US Remote) Anomali

SFDC Architect Diverse Lynx, LLC

Enterprise Architect SHI International Corp

JSE Lead Open Systems Architect (Fort Worth, TX, US, 76155) FlightSafety International

Cloud Solution Architect – Security Invoke

Distributed Systems Integration Architect ( Leadership Role) - ( US Citizen) Blue Yonder

Solution Architect in Memorial Office (West), Texas | Careers at S&B Houston S&B Engineers and Constructors

Lead Security Architect Humana Inc

Cyber Architect Diverse Lynx, LLC

Principal Architect, BU Vistra Corp

Associate Director, Lead Data Architect - Databricks Guidehouse Inc

Manager, Solutions Architect KPMG International Cooperative

Hardware Security Architect NXP Semiconductor, Inc.

DPU IO Architect, Infrastructure Silicon Meta Platforms Inc

DPU Networking Architect, Infrastructure Silicon Meta Platforms Inc

DPU Performance Architect, Infrastructure Silicon Meta Platforms Inc

Snowflake Data Architect Diverse Lynx, LLC

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