UNKNOWN

FEED

This is a highly visible technical and leadership role where you will influence DFT architecture, lead complex execution across teams, drive methodology improvements, mentor engineers, and support successful silicon bring-up, yield ramp, and production quality. Experience developing DFT methodologies for low-power designs, including UPF-aware test strategies, power domain testing, isolation, retention, and test-mode power management.

Velaura AI Inc

DFT Engineer (Architect / Manager / Sr. Manager)

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GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies. The position requires deep technical expertise, hands-on research leadership, and the ability to translate emerging quantum concepts into practical engineering solutions.

YEAR

GlobalFoundries Inc

Quantum Ion Trap Technology Architect

With a proven track record in architecting and delivering cutting-edge solutions for complex system-level challenges, you possess deep expertise in semiconductor, EDA, or high-tech environments. You are adept at translating customer requirements into robust, scalable architectures that anticipate future needs, and you excel at navigating ambiguity to deliver strategic clarity.

NXP Semiconductors NV

Software Architect

Analyze performance of current and future SmartNIC/IPU/DPU architectures with focus on end-to-end transaction flows, host-to-DPU offloading options, evaluation of SoC architectural options Quantify architectural/micro-architectural trade-offs wrt PPA to inform and guide design decisions Analyze and characterize DPU workloads to abstract key performance-relevant behaviors and incorporate into representative models and synthetic benchmarks Develop and enhance performance models, simulation tools, and methodologies to evaluate future DPU architectures Drive RTL performance validation, including development of comprehensive performance test plans, coverage criteria, and correlation of RTL results against architectural models Correlate pre-silicon performance projections with post-silicon measurements and drive methodology improvements based on findingsBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of relevant industry experience in developing analytical/tool based models and performance analysis with focus on networking and storage architectures Detailed understanding of DPU architectures: network virtualization, storage disaggregation, networking and storage protocols such as RoCE, NVMe, fabric architectures Experience in workload analysis and characterization, and abstracting key performance features into models for analysis Proficiency in languages for model development (e.g. Python, C/C++, SystemC) Experience with data center workloads and benchmarking methodologies Experience with RTL performance validation, including authoring and executing performance test plans and correlating pre-silicon performance models with post-silicon measurements Experience driving analysis independently and influencing architectural direction through data PhD in Computer Science, Computer Engineering or Electrical Engineering 15+ years of relevant industry experience in developing analytical/tool based models and performance analysis with focus on networking and storage architectures Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs Experience with post-silicon performance validation and model-to-hardware correlation methodologies Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysis Experience with GPU, machine learning, multi-threaded programming paradigm Experience with high-level synthesis, power-performance-area trade-off analysis, or PPA-driven microarchitectural optimizationMeta builds technologies that help people connect, find communities, and grow businesses.

Meta Platforms Inc

DPU Performance Architect, Infrastructure Silicon

Support post-silicon bring-up of the I/O subsystemBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of relevant industry experience architecting I/O and system subsystems and their hardware/software interfaces - register and programming models, DMA and descriptor interfaces, doorbells, and offload interfaces - for NIC/DPU or comparable ASICs Experience with PCIe data link and transport protocols, including TLP formats, transaction types (posted/non-posted/completions), and ordering rules Experience with I/O virtualization technologies such as SR-IOV and SIOV Experience with PCIe capabilities such as Advanced Error Reporting, Downstream Port Containment, and Integrity and Data Encryption Experience with on-chip scheduling and arbitration architectures and quality-of-service mechanisms - transaction/packet schedulers, arbiters, traffic shapers, and rate limiters (meters/policers, token buckets) - and their impact on latency, fairness, bandwidth partitioning, and throughput Experience with symmetric and asymmetric cryptography concepts and inline data encryption (e.g., AES-XTS, AES-GCM) Experience with x86 and/or ARM system architecture, including virtualization technologies, IOMMUs, and interrupt virtualization Experience with data center workloads and their I/O characteristics Experience driving architectural decisions independently and influencing their direction through data PhD in Computer Science, Computer Engineering or Electrical Engineering 15+ years of relevant industry experience architecting I/O and system subsystems and hardware/software interfaces for NIC/DPU or comparable ASICs Experience designing PCIe endpoints and root complexes Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysis Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs Experience with system-management concepts including server/BMC interactions, and protocols such as I2C, I3C, USB/Ethernet, USB/MCTP, and SPI/eSPI Experience designing high-performance DMA engines and offload accelerators, such as for cryptography and compression Experience with post-silicon performance validation and model-to-hardware correlation methodologies Understanding of Confidential Computing use cases and the related PCIe protocols -- Data Object Exchange (DOE), Security Protocol and Data Model (SPDM), Management Component Transport Protocol (MCTP), and TEE Device Interface Security Protocol (TDISP)Meta builds technologies that help people connect, find communities, and grow businesses. Own the I/O subsystem architecture for our DPUs - PCIe, DMA and offload engines, I/O virtualization, confidential computing, and system management -- from early path-finding through silicon bring-up Decide what runs in hardware, what runs in firmware, and what stays in host software, and design the interfaces between them Define the hardware/software interface - register and programming models, descriptor and doorbell interfaces, error and interrupt models, and the offload interfaces firmware and drivers build on Work closely with firmware, driver, and software teams so the interface is clean, efficient, and genuinely usable, and evolve it as their needs change Weigh the performance, power, and area trade-offs behind your choices and back them with data, partnering with performance modeling where deeper analysis is needed Work closely with design, DV, and PD teams on feature definition and PPA tradeoff; refine architecture to meet the design and PD constraints.

DPU IO Architect, Infrastructure Silicon

Design and evolve enterprise identity and endpoint platforms, including Active Directory, Microsoft Entra ID, Microsoft 365, SAML, OIDC, OAuth, SCIM, PKI, privileged access, Intune, Configuration Manager, JAMF, Windows, and macOS management. Define enterprise infrastructure architecture across AWS, on-premises, virtualization, Windows, Linux, identity, storage, backup, endpoint, and SaaS environments, including current-state, transitional, and target-state designs.

Bloom Energy is changing the way the world generates and consumes energy.
 
 Our unique on-site power generation systems utilize an innovative new fuel cell technology with roots in NASA's Mars program.
 Derived from a common sand-like powder, and leveraging breakthrough advances in materials science, our technology is able to produce clean, reliable, affordable power,... practically anywhere,... from a wide range of renewable or traditional fuels.
 Our Energy Serversâ„¢ are among the most efficient energy generators on the planet; providing for significantly reduced electricity costs and dramatically lower greenhouse gas emissions.
 By generating power on-site, where it is consumed, Bloom Energy offers increased electrical reliability and improved energy security, providing a clear path to energy independence.
 Founded in 2001, Bloom Energy is headquartered in Sunnyvale, California.
 
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Bloom Energy Corp

Principal IT Systems Architect

Technical Proficiency: Strong knowledge of security frameworks (e.g., NIST, ISO 27001) and proficiency in security technologies such as firewalls, web proxy, intrusion detection/prevention systems, SASE, Secure Browser, XDR, DLP, CASB, CNAPP, IAM. Our cutting-edge solutions enable unparalleled “time-to-power” capabilities, reliability, and sustainability, ensuring our customers remain ahead in a world where soaring energy demand and intensifying energy scarcity are rapidly becoming the new norm.

Bloom Energy

Senior Staff Engineer, Security Architect

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Were looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Google LLC

Senior Accelerators Systems Software Architect, AI Transformation

Deliver solutions to complex CPU performance, microarchitecture design, tool infrastructure, and methodology problems that are ambiguous or lack clear precedent. Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Senior CPU Performance Architect

Proven track records of expertise in digital design including microarchitecture specification development, system modeling, RTL logic design, synthesis, timing closure and power-performance-area (PPA) analysis. As a global leader in HBM, DRAM, and NAND flash technologies, we develop the advanced memory solutions powering everything from advanced mobile technology to massive AI data centers.

SK hynix

AI Memory Solution Architect

battery life, thermals, silicon roadmaps, power load profiles) MS/PhD in Electrical Engineering, Computer Engineering, or other related technical field, or equivalent industry experience Experience in one or more of the following areas: firmware development, programming, computer vision, Android/Zephyr OSs, game development and complex sensing systems Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologies Experience with AR/VR or systems aimed at capturing/processing/delivering audio visual, IMU or other positional data streams Experience creating system models to analyze system compute, latency and communication interface bandwidths across multiple subsystems within a heterogeneous compute environment in order to define the system architecture to meet the overall goals of the product definition Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements) Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews) Understanding of memory subsystems including mass storage and filesystem as well as volatile memory, memory management and its impacts on overall system performanceMeta builds technologies that help people connect, find communities, and grow businesses. Own platform system architecture definition across one or more subsystems including compute/memory, displays/optics, electrical engineering, sensors, audio, wireless connectivity, I/O and firmware from initial conception through prototyping, product development, and production ramp Across a portfolio of products, work with other system architects and SW engineering teams to understand and document requirements for workloads that need to be supported.

Wearables Systems Architect

This will span defining our strategic bets, industry and platform-led business plays, orchestration model, propensity modeling, field activation, offers and incentives, business value thought leadership, partner and ecosystem execution, in order to reach our growth goals. As a Practice Architect, within Google Cloud, you will bring your experience and thought leadership and operational mindset to help drive outlook, mission, and strategy for the Data Analytics, Databases, Knowledge Catalog Go-To-Market (GTM) motion.

Practice Architect, Agentic Data Cloud

We are seeking a highly experienced Design Verification Architect to lead the definition and execution of scalable, reusable, and high-quality verification strategies for next-generation SoCs targeting AI, HPC, and Networking applications . This role requires deep expertise in verifying large and complex SoCs and a passion for building next-gen verification platforms, leveraging automation, portability, and AI-driven methodologies .

TYLsemi

Design Verification Architect

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As Powertrain Architect, you will evaluate and size the hybrid-electric propulsion system for a next-generation eVTOL - spanning combustion engine selection, electromagnetic sizing, thermal management, and battery behavior - and contribute the resulting models into Archer''s broader vehicle-level sizing and optimization stack. Evaluate and trade hybrid-electric powertrain architectures (series, parallel, turbo-electric), integrating battery energy storage and electric motors/inverters, with a turboshaft-driven generator as one of the configurations considered.

Archer Aviation Inc

Powertrain Architect - Hybrid-Electric Propulsion

You bring both theoretical rigor and practical experience to every challenge, leveraging your modeling skills in MATLAB/Simulink and your hands-on knowledge of circuit design and DSP. The team is a blend of experienced analog and digital designers, hardware engineers, and system architects, united by a shared vision to advance silicon IP technology.

Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure.
 
Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools for silicon chip design, verification, IP integration, and application security testing. Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything.

Synopsys Inc

SerDes/DSP System, Sr Architect - 18614

The base salary range is 184,000 USD - 287,500 USD for Level 4, and 224,000 USD - 356,500 USD for Level 5. Understand and help drive implementation of bus protocols, networking protocols, memory access and security solutions across a range of products.

Visualize your future . . . We Do 
NVIDIA is the world leader in graphics processing technologies, creating innovative, industry-changing products for computing, consumer electronics, and mobile devices. NVIDIA products are transforming visually-rich applications such as video games, film production, broadcasting, industrial design, space exploration, and medical imaging. We invest in our people and our technologies, support and fund industry research around the world, and consistently deliver high-quality products. NVIDIA's culture promotes and inspires a team of world-class employees to be at the top of their game. We've created an environment where talents are recognized and collaboration is valued. Our employees are shaping the world of tomorrow. . . today. We invite you to explore the opportunities available at NVIDIA to see what your future may hold.

Nvidia

AI Hardware Architect

TeaCliententer implementation/support experience in BOM Management, Change Management, Security, SSO/LDAP Integration, Material Management (IMM), TcRA, Substance Compliance, and TeaCliententer Manufacturing. Must Have / Key Skills: 6 years relevant experience with Siemens TeaCliententer, including implementation, development-team coordination, and customer management.

Looking for a great job? Join eTeam. We’re looking for talented staffing professionals to join our staff. We also provide contract assignments and full-time jobs at Fortune 2000 Companies. We’ve been named one of the best companies to work for by Staffing Industry Analysts and New Jersey Business.

eTeam Inc.

Teamcenter Integration Architect

jobdiva

If you have expertise in Team center Architect, implementation and PLM processes. Looking for a Team Center PLM Functional Architect.

Tata Consultancy Services Ltd

Team Center PLM Functional Architect

Our specialized experience includes design for data centers, healthcare, science and technology, high-rise buildings, clean energy, education, and other building types as well as structural and building sciences, infrastructure asset management, advanced robotics, and more. Our technical expertise is paired with an exceptional team of business development, human resources, finance and accounting, information technology, and marketing professionals, all of whom play a key role in bringing our commitments to life every day.

Salas O'Brien

Architect

Lens integrates our real-world data and advanced algorithms into a cloud-based Software-as-a-Service platform, transforming hypothesis generation and testing into a closed-loop process a single researcher can do in minutes, not an open-ended process a research team works on for months or years. On the Lens team at Tempus, we are building a data science platform to make it easier for researchers both inside and outside of Tempus to answer important questions in precision medicine using Tempus' multi-modal clinical, imaging, and molecular data.

Architect Jobs in San Jose, CA

DFT Engineer (Architect / Manager / Sr. Manager) Velaura AI Inc

Quantum Ion Trap Technology Architect GlobalFoundries Inc

Software Architect NXP Semiconductors NV

DPU Performance Architect, Infrastructure Silicon Meta Platforms Inc

DPU IO Architect, Infrastructure Silicon Meta Platforms Inc

Principal IT Systems Architect Bloom Energy Corp

Senior Staff Engineer, Security Architect Bloom Energy

Senior Accelerators Systems Software Architect, AI Transformation Google LLC

Senior CPU Performance Architect Google LLC

AI Memory Solution Architect SK hynix

Wearables Systems Architect Meta Platforms Inc

Practice Architect, Agentic Data Cloud Google LLC

Design Verification Architect TYLsemi

Powertrain Architect - Hybrid-Electric Propulsion Archer Aviation Inc

SerDes/DSP System, Sr Architect - 18614 Synopsys Inc

AI Hardware Architect Nvidia

Teamcenter Integration Architect eTeam Inc.

Team Center PLM Functional Architect Tata Consultancy Services Ltd

Architect Salas O'Brien

Solution Architect Tempus

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