UNKNOWN

FEED

You will operate more like a senior technical partner than a traditional pre-sales architect: build trust with C-suite and technical leaders, bring a strong point of view on where AI can create meaningful business value, shape the solution with the customer, and stay accountable for the technical relationship beyond signature. You will lead the technical arc of an account from early technology conversations and problem shaping through architecture, feasibility, and SOW; for qualified late-stage pursuits, you will partner with forward deployed engineers to drive implementation of solutions.

YEAR

Distyl AI

Enterprise AI Architect

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We are a team of previous Stanford professors, SAIL researchers, Olympiad medalists (IPhO, IOI, etc.), the inventors of IC3 and the Murphi verification system, CTOs of Synopsys & GlobalFoundries, Head of Sales & CRO of Cadence, former US Secretary of Defense, National Security Advisor, and Senior Foreign-Policy Advisor to four US presidents. You'll work on real silicon programs with the world's largest semiconductor companies while shaping how Voltai's AI reasons about architecture, trade-offs, and design intent.

Voltai

Chip Architect

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They bring deep experience designing and governing APIs across heterogeneous systems-proprietary CAD tools, simulation engines, layout databases, EM/optical solvers, test platforms, and CI/CD pipelines-while defining canonical data models that preserve design intent and traceability from schematic through layout, extraction, verification, and tape-out. The ideal candidate combines architectural rigor with pragmatism: able to reduce toolchain chaos into scalable, observable, and secure integration platforms that enable automation, reproducibility, and rapid innovation across PIC, passive, and active IC design teams.

PsiQuantum

Senior Integration/Api Architect

Your job responsibilities as a Memory Subsystem Architect will be providing technical leadership through all phases of Baidu’s AI SoC development, but primarily focused on unified memory space architecture design for Baidu AI accelerator SoC. Work with Hardware design, verification, emulation, and validation teams to build and test the hardware architecture, performance and functionality.

Baidu USA

SoC Memory Subsystem Architect

An employee's pay position within the salary range may be based on several factors including but not limited to (1) relevant education; qualifications; certifications; and experience; (2) skills, ability, knowledge of the job; (3) performance, contribution and results; (4) geographic location; (5) shift; (6) internal and external equity; and (7) business and organizational needs. We combine deep engineering expertise with global-scale manufacturing to deliver the storage systems that make AI possible, powering hyperscale data centers, cloud platforms, and enterprise infrastructure worldwide.

We’ve been storing the world’s data for more than 50 years. Once, storage was the most important thing we could do for data. Now, we’re helping the world capture, preserve, access and transform data in a way only we can.
 The most game-changing companies, consumers, professionals, and government organizations come to us for the technologies and solutions needed to bring meaning and value to their ever-increasing diversity of data.
 But we can’t do it alone. Today’s exceptional data challenges require your unique skills. You can be the next big thing in data.
 Western Digital® data-centric solutions are comprised of the Western Digital, G-Technology™, SanDisk® and WD® brands.

Western Digital Corp

Principal Full Stack Developer & Solutions Architect - AI, Data & Cloud

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Design and deliver integration architectures that connect interface.ai 's AI platform to a customer's core banking systems (Jack Henry, Fiserv, FIS, Corelation, or equivalent), telephony infrastructure, and contact center stack — accounting for real-world constraints like latency, legacy data models, and compliance requirements, not just demo conditions. Telephony and CCaaS integration fluency — has designed or debugged live implementations involving SIP trunking, PSTN routing, IVR handoff patterns, or voice AI engine connectivity (Genesys, Avaya, Five9, NICE, Twilio, or equivalent).

interface.ai

Solutions Architect

In this role you lead the functional design of a defined workstream or capability area within a larger Salesforce Life Sciences program - running requirements and design sessions, translating business processes into platform solutions, and making day-to-day design decisions within the architecture direction set by senior architecture leadership. We Are: Accenture is a leading global professional services company that helps the world's leading businesses, governments and other organizations build their digital core, optimize their operations, accelerate revenue growth and enhance citizen services-creating tangible value at speed and scale.

Accenture Plc

Salesforce Patient Services Architect

Own the RAS and debug architecture for our DPUs - error detection, correction, and reporting, FIT budgeting, and the trace, debug, and telemetry infrastructure - from early path-finding through silicon bring-up Set FIT-rate targets from the intended usages and deployment models, and budget them across the design - memories, logic, on-chip interfaces, and links Define the error detection, correction, reporting, and containment architecture -- parity, ECC/SECDED, poisoning and poison propagation, error logging, and how errors are surfaced to firmware, host software, and platform management Define the trace, debug, and performance-monitoring architecture for post-silicon debug and for software and firmware debugging - on-chip trace, event and counter telemetry, crash and state capture, and the JTAG/debug-access model Decide what belongs in hardware versus firmware versus software, and define how the hardware presents itself to them - register and programming models, error and interrupt models, and trace/telemetry interfaces Work closely with design, DV, and PD teams on feature definition and PPA tradeoff; refine architecture to meet the design and PD constraints. Support post-silicon bring-upBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of relevant industry experience architecting RAS and debug/trace architectures and their hardware/software interfaces for NIC/DPU or comparable ASICs Experience with RAS concepts: FIT-rate estimation and budgeting, failure modes (including silent data corruption), error detection, correction, and containment, and reliability targets for data center deployments.

Meta Platforms Inc

DPU RAS and Debug Architect, Infrastructure Silicon

Analyze performance of current and future SmartNIC/IPU/DPU architectures with focus on end-to-end transaction flows, host-to-DPU offloading options, evaluation of SoC architectural options Quantify architectural/micro-architectural trade-offs wrt PPA to inform and guide design decisions Analyze and characterize DPU workloads to abstract key performance-relevant behaviors and incorporate into representative models and synthetic benchmarks Develop and enhance performance models, simulation tools, and methodologies to evaluate future DPU architectures Drive RTL performance validation, including development of comprehensive performance test plans, coverage criteria, and correlation of RTL results against architectural models Correlate pre-silicon performance projections with post-silicon measurements and drive methodology improvements based on findingsBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of relevant industry experience in developing analytical/tool based models and performance analysis with focus on networking and storage architectures Detailed understanding of DPU architectures: network virtualization, storage disaggregation, networking and storage protocols such as RoCE, NVMe, fabric architectures Experience in workload analysis and characterization, and abstracting key performance features into models for analysis Proficiency in languages for model development (e.g. Python, C/C++, SystemC) Experience with data center workloads and benchmarking methodologies Experience with RTL performance validation, including authoring and executing performance test plans and correlating pre-silicon performance models with post-silicon measurements Experience driving analysis independently and influencing architectural direction through data PhD in Computer Science, Computer Engineering or Electrical Engineering 15+ years of relevant industry experience in developing analytical/tool based models and performance analysis with focus on networking and storage architectures Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs Experience with post-silicon performance validation and model-to-hardware correlation methodologies Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysis Experience with GPU, machine learning, multi-threaded programming paradigm Experience with high-level synthesis, power-performance-area trade-off analysis, or PPA-driven microarchitectural optimizationMeta builds technologies that help people connect, find communities, and grow businesses.

DPU Performance Architect, Infrastructure Silicon

Support post-silicon bring-up of the I/O subsystemBachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 8+ years of relevant industry experience architecting I/O and system subsystems and their hardware/software interfaces - register and programming models, DMA and descriptor interfaces, doorbells, and offload interfaces - for NIC/DPU or comparable ASICs Experience with PCIe data link and transport protocols, including TLP formats, transaction types (posted/non-posted/completions), and ordering rules Experience with I/O virtualization technologies such as SR-IOV and SIOV Experience with PCIe capabilities such as Advanced Error Reporting, Downstream Port Containment, and Integrity and Data Encryption Experience with on-chip scheduling and arbitration architectures and quality-of-service mechanisms - transaction/packet schedulers, arbiters, traffic shapers, and rate limiters (meters/policers, token buckets) - and their impact on latency, fairness, bandwidth partitioning, and throughput Experience with symmetric and asymmetric cryptography concepts and inline data encryption (e.g., AES-XTS, AES-GCM) Experience with x86 and/or ARM system architecture, including virtualization technologies, IOMMUs, and interrupt virtualization Experience with data center workloads and their I/O characteristics Experience driving architectural decisions independently and influencing their direction through data PhD in Computer Science, Computer Engineering or Electrical Engineering 15+ years of relevant industry experience architecting I/O and system subsystems and hardware/software interfaces for NIC/DPU or comparable ASICs Experience designing PCIe endpoints and root complexes Experience with hardware description languages (e.g., SystemVerilog, VHDL) and simulation environments used in ASIC development flows Experience developing Python-based automation pipelines for simulation orchestration, regression testing, and performance data analysis Experience building or scaling performance modeling infrastructure for hyperscale data center ASICs, including network, storage, or AI inference accelerator designs Experience with system-management concepts including server/BMC interactions, and protocols such as I2C, I3C, USB/Ethernet, USB/MCTP, and SPI/eSPI Experience designing high-performance DMA engines and offload accelerators, such as for cryptography and compression Experience with post-silicon performance validation and model-to-hardware correlation methodologies Understanding of Confidential Computing use cases and the related PCIe protocols -- Data Object Exchange (DOE), Security Protocol and Data Model (SPDM), Management Component Transport Protocol (MCTP), and TEE Device Interface Security Protocol (TDISP)Meta builds technologies that help people connect, find communities, and grow businesses. Own the I/O subsystem architecture for our DPUs - PCIe, DMA and offload engines, I/O virtualization, confidential computing, and system management -- from early path-finding through silicon bring-up Decide what runs in hardware, what runs in firmware, and what stays in host software, and design the interfaces between them Define the hardware/software interface - register and programming models, descriptor and doorbell interfaces, error and interrupt models, and the offload interfaces firmware and drivers build on Work closely with firmware, driver, and software teams so the interface is clean, efficient, and genuinely usable, and evolve it as their needs change Weigh the performance, power, and area trade-offs behind your choices and back them with data, partnering with performance modeling where deeper analysis is needed Work closely with design, DV, and PD teams on feature definition and PPA tradeoff; refine architecture to meet the design and PD constraints.

DPU IO Architect, Infrastructure Silicon

Were looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Google LLC

Senior Accelerators Systems Software Architect, AI Transformation

Deliver solutions to complex CPU performance, microarchitecture design, tool infrastructure, and methodology problems that are ambiguous or lack clear precedent. Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Senior CPU Performance Architect

For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. Experience developing reference designs or new infrastructure architectures within a hyperscaler, data center operator, advanced engineering organization, or major design consultancy.

OpenAI

Data Center Infrastructure Architect

Design and evolve enterprise identity and endpoint platforms, including Active Directory, Microsoft Entra ID, Microsoft 365, SAML, OIDC, OAuth, SCIM, PKI, privileged access, Intune, Configuration Manager, JAMF, Windows, and macOS management. Define enterprise infrastructure architecture across AWS, on-premises, virtualization, Windows, Linux, identity, storage, backup, endpoint, and SaaS environments, including current-state, transitional, and target-state designs.

Bloom Energy is changing the way the world generates and consumes energy.
 
 Our unique on-site power generation systems utilize an innovative new fuel cell technology with roots in NASA's Mars program.
 Derived from a common sand-like powder, and leveraging breakthrough advances in materials science, our technology is able to produce clean, reliable, affordable power,... practically anywhere,... from a wide range of renewable or traditional fuels.
 Our Energy Serversâ„¢ are among the most efficient energy generators on the planet; providing for significantly reduced electricity costs and dramatically lower greenhouse gas emissions.
 By generating power on-site, where it is consumed, Bloom Energy offers increased electrical reliability and improved energy security, providing a clear path to energy independence.
 Founded in 2001, Bloom Energy is headquartered in Sunnyvale, California.
 
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Bloom Energy Corp

Principal IT Systems Architect

You'll operate as a subject matter expert on platform modernization within a small team of architects, applying AI-assisted and Spec-Driven Development (SDD) practices to help teams build new components using our Target State Architecture stack of technologies. We offer all of our global employees generous and flexible time off with 2 company-wide closure weeks, Taskrabbit product stipends, wellness + productivity + education stipends, IKEA discounts, reproductive health support, and more.

Taskrabbit

Staff Software Architect

GreenHouseAPI

For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non-public information. Build and deliver customer-facing demos, prototypes, workshops, proofs of concept, and reference architectures using OpenAI APIs, Codex, agents, scripts, CLIs, GitHub workflows, CI/CD systems, logs, tickets, scanners, and common security tools.

Applied AI Architect, Cyber

We're looking for a candidate to define products, shape architecture strategy, and support the launch of Point-of-Load (PoL) power solutions that meet latest system-level requirements. This role is pivotal in defining next-generation Point of Load (PoL) solutions for APS, driving innovation in advanced power management with System-in-Package (SiP) integration.

NXP Semiconductors NV

Systems IC Architect

With a proven track record in architecting and delivering cutting-edge solutions for complex system-level challenges, you possess deep expertise in semiconductor, EDA, or high-tech environments. You are adept at translating customer requirements into robust, scalable architectures that anticipate future needs, and you excel at navigating ambiguity to deliver strategic clarity.

Software Architect

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies. The position requires deep technical expertise, hands-on research leadership, and the ability to translate emerging quantum concepts into practical engineering solutions.

GlobalFoundries Inc

Quantum Ion Trap Technology Architect

Designing and implementing end-to-end enterprise architectures, system integrations, including autonomous workflows, APIs, data pipelines, and secure, scalable platforms; Supply Chain Management, including AI/ML Luminate Demand Edge (LDE), Luminate Allocation (LA), SCPO Demand and Fulfillment, Inventory Optimization (IO), Probabilistic Perpetual Inventory (PPI), and Portfolio Merchandise Management (PMM). As an Enterprise Solution Architect, you will serve as a trusted advisor to customers and internal stakeholders, leading the architecture, design, and implementation of complex enterprise-scale supply chain solutions.

Architect Jobs in Fremont, CA

Enterprise AI Architect Distyl AI

Chip Architect Voltai

Senior Integration/Api Architect PsiQuantum

SoC Memory Subsystem Architect Baidu USA

Principal Full Stack Developer & Solutions Architect - AI, Data & Cloud Western Digital Corp

Solutions Architect interface.ai

Salesforce Patient Services Architect Accenture Plc

DPU RAS and Debug Architect, Infrastructure Silicon Meta Platforms Inc

DPU Performance Architect, Infrastructure Silicon Meta Platforms Inc

DPU IO Architect, Infrastructure Silicon Meta Platforms Inc

Senior Accelerators Systems Software Architect, AI Transformation Google LLC

Senior CPU Performance Architect Google LLC

Data Center Infrastructure Architect OpenAI

Principal IT Systems Architect Bloom Energy Corp

Staff Software Architect Taskrabbit

Applied AI Architect, Cyber OpenAI

Systems IC Architect NXP Semiconductors NV

Software Architect NXP Semiconductors NV

Quantum Ion Trap Technology Architect GlobalFoundries Inc

Enterprise Solution Architect ( Supply Chain) Blue Yonder

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