Verification Engineer – Silicon / Semiconductor

Simple Solutions

  • Santa Clara, Santa Clara
  • 30+ days ago

    Highlights

    We are seeking a Verification Engineer to join our silicon development team, responsible for ensuring the functional correctness and quality of complex ASIC/SoC designs. You will work closely with design, architecture, and validation teams to develop robust verification environments and drive coverage closure.

    Numbers & Facts

    LocationSanta Clara, Santa Clara
    Websitehttp://simplesolutions.us

    Description

    We are seeking a Verification Engineer to join our silicon development team, responsible for ensuring the functional correctness and quality of complex ASIC/SoC designs. This role is critical in validating next-generation chips used in high-performance computing, AI/ML, networking, or consumer electronics.

    You will work closely with design, architecture, and validation teams to develop robust verification environments and drive coverage closure.

    Key Responsibilities

    • Develop and execute verification plans for ASIC/SoC components and subsystems
    • Build and maintain SystemVerilog/UVM-based testbenches
    • Create directed and constrained-random tests to validate design functionality
    • Debug and root-cause RTL issues in collaboration with design engineers
    • Drive functional coverage and ensure verification completeness
    • Perform regression testing and analyze results for failures and gaps
    • Develop and use assertions (SVA) for design verification
    • Contribute to verification methodology improvements and automation
    • Support post-silicon validation teams with test scenarios and debug insights

    Required Qualifications (MUST-HAVE)

    • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
    • 3–10+ years of experience in ASIC/SoC verification
    • Strong expertise in SystemVerilog and UVM methodology
    • Experience with RTL design concepts (Verilog/VHDL)
    • Solid debugging skills in simulation environments
    • Experience with EDA tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa)
    • Understanding of functional coverage and verification metrics

    Preferred Qualifications (NICE-TO-HAVE)

    • Experience with formal verification tools
    • Knowledge of protocols (PCIe, Ethernet, AXI, DDR, USB, etc.)
    • Scripting skills in Python, Perl, or Tcl
    • Experience with emulation or FPGA prototyping
    • Exposure to low-power verification (UPF/CPF)
    • Background in AI/ML accelerators or GPU architectures

    Key Skills

    • Strong problem-solving and debugging mindset
    • Ability to work in a fast-paced, cross-functional environment
    • Clear communication with design and architecture teams
    • Attention to detail and quality

    Typical Day-to-Day

    • Running regressions and debugging failing test cases
    • Writing new UVM test sequences and coverage models
    • Collaborating with RTL designers on bug fixes
    • Reviewing verification plans and coverage reports
    • Participating in design and verification reviews


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