Create high-performance FPGA solutions to support next-generation modem systems from LEO satellites. This is a unique opportunity to define and implement a state-of-the-art wireless communication system with a focus on an ultra-reliable low-latency, high-throughput physical layer (PHY). The FPGA Design Engineer will work closely with systems teams to define, develop, and release FPGA-based signal processing and modem solutions using latest generation hardware and modern design methodologies.
Key job responsibilities:
• End-to-End RTL Development: Create and release RTL code through the full development lifecycle: system architecture definition, RTL design, physical implementation, timing closure, and simulation validation. • System Integration: Collaborate with Digital Communications and RF system architects to implement complex logic functions such as signal detection and synchronization, channel coding (LDPC/Polar), beamforming, or massive MIMO processing. • Cross-Functional Collaboration: Work with HW, FW, and SW teams to bring up and test integrated systems combining FPGA, RF front-ends, and networking stacks. • Architectural Trade-offs: Drive trade-off analysis to optimize FPGA resources for cost, size, power, and performance to meet stringent 5G latency and throughput requirements. • Validation: Conduct lab-based silicon validation using high-speed signal generators and analyzers to ensure modem performance meets throughput and reliability metrics.
Export Control Requirement
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.