Senior Solution Architect

Job Description

Senior Solution Architect

Job Summary

A Physical Design Chip Lead (or Full-Chip Physical Design Lead) is a highly experienced VLSI professional who owns the end-to-end digital implementation and tape-out delivery of an entire Integrated Circuit (IC) or System-on-Chip (SoC). This role requires a balance of expert-level technical execution (RTL-to-GDSII) and project leadership to guide execution teams, manage schedule risks, and bridge the gap between architecture and silicon manufacturing.

Key Responsibilities

Job summary: We are seeking a highly technical and execution-driven Physical Design Chip Lead to spearhead the structural design, implementation, and physical sign-off of our next-generation, high-performance SoCs. In this role, you will own the entire full-chip physical design lifecycle-from early architectural feasibility, floorplanning, and synthesis through final GDSII tape-out. You will lead a team of talented physical design engineers, establish sign-off methodologies, and collaborate directly with architects, front-end designers, and foundry partners to deliver best-in-class Power, Performance, and Area (PPA) on advanced process nodes.

Skill Requirements

Drive the execution of the entire hierarchical RTL-to-GDSII physical design flow, including synthesis, floorplanning, place & route (PnR), clock tree synthesis (CTS), timing closure, and physical verification.

• Define the physical implementation strategy, schedule milestones, and allocate resources across block-level and full-chip integration tasks. Identify and mitigate technical or schedule risks early.
• Partner with SoC architects to conduct early feasibility studies. Drive top-level floorplanning, package/bump placement, macro integration, and full-chip Power Distribution Network (PDN) definitions.
• Establish strict sign-off criteria and methodologies for the project across all domains: Static Timing Analysis (STA), Electromigration and IR Drop (EMIR), Low Power Compliance (VCLP/UPF), and Physical Verification (DRC/LVS/ERC).
• Act as the primary engineering bridge between RTL Front-End, Design Verification (DV), DFT, Packaging, Signal/Power Integrity, and external Silicon Foundries.
• Lead the final closure push for the full-chip database, auditing waivers, reviewing engineering change orders (ECOs), and authorizing final tape-out release.
• Guide, mentor, and perform technical reviews for junior and mid-level physical design engineers to elevate the teams technical capabilities

Other Requirements

• with a proven track record of leading or co-leading complex full-chip SoC tape-outs.
• Core flow mastery: Synopsys (Fusion Compiler, IC Compiler II, PrimeTime, StarRC, VC LP) or Cadence (Innovus, Tempus, Quantus, Pegasus, Voltus)
• Advanced nodes: Extensive tape-out experience on sub-7nm FinFET or GAA process nodes (e.g., TSMC/Intel/Samsung N5, N3, N2) handling tight design rules and complex multi-patterning layouts.
• advanced clock-tree architectures, hierarchical UPF low-power designs, and chip-package co-design.
• Proficient in TCL/python/Shell

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Information at a Glance

Why HCLTech?

At HCLTech, youll supercharge your potential. Youll find your career. And youll find your spark. All at a place that knows that helping its customers stay on top starts by putting its people first.

HCLTech is a global technology company, home to more than 223,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending June 2026 totaled $14.8 billion.