Senior Lead Memory Circuit Design Engineer

Location: Mesa, AZ (preferred; CA candidates considered)
Role:
Lead end-to-end memory subsystem design from architecture through tapeout for advanced mixed-signal SoCs, collaborating with Analog, Digital, Verification, and Layout teams.

Key Responsibilities:

• Own memory architecture, circuit design, verification, signoff, and tapeout.

• Design/optimize memory arrays, sense amplifiers, references, read/write circuits, decoders, and datapaths.

• Perform SPICE simulations, PVT/temperature sweeps, Monte Carlo, mismatch, and reliability analysis.

• Review chip-level timing issues, margins, waveforms, and signoff results.

• Partner with Layout on floorplanning, parasitics, EM/IR, density, antenna, and signoff.

• Mentor engineers and lead cross-functional execution.

Required Qualifications:

• BSEE/MSEE/PhD or equivalent.

• 15+ years of memory circuit design experience, including SRAM and NVM.

• Multiple successful tapeouts with subsystem/block ownership.

• Strong mixed-signal, sense amplifier, reference generation, and memory architecture expertise.

• Experience with Cadence/Synopsys and SPICE tools such as HSPICE, Spectre, or PrimeSim.

• Strong leadership and mentoring skills.

Preferred:

• MRAM/RRAM or other resistive/NVM experience.

• Silicon characterization and post-silicon debug.

• Crosspoint-style memory architectures.

• EM/IR, ESD, latch-up, and reliability signoff experience.

W3Global was established in 2006 in Fremont, CA with a vision: simplify the recruiting process and develop an industry-disrupting platform to connect candidates with clients. Our cutting-edge Applicant Tracking System enables us to find the right person for the right job, creating value for job seekers and employers. While W3Global initially focused on IT staffing, we have expanded the business to serve many other industries, including accounting and finance, legal, engineering, human resources, government and more.

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