Nice to have: semiconductor capital equipment or EUV/DUV source exposure; Python test automation; SECS/GEM or EtherCAT; prior work in ITAR/EAR environment. Integrate the bench with the client's hardware and software build targets; run closed-loop tests and lead defect triage.
Numbers & Facts
Location
San Diego, CA
Website
http://www.zealogics.com
Description
Define the HIL bench architecture: real-time target selection, I/O mapping, signal conditioning, safety interlocks, and fidelity targets
Develop and validate plant and power-electronics models in OPAL-RT (RT-LAB / HYPERSIM) and MATLAB/Simulink
Integrate the bench with the client's hardware and software build targets; run closed-loop tests and lead defect triage
Own the acceptance specification and drive it to sign-off with client engineering
Direct the offshore controls, test and software engineers: work breakdown, reviews, weekly progress reporting to the client
Act as custodian for export-controlled technical data; ensure only cleared individuals access controlled material
What you bring
8+ years in controls, test or systems engineering for high-power electronics, plasma, laser, or precision motion systems
3+ years hands-on with OPAL-RT (or dSPACE / Speedgoat / NI VeriStand) HIL development
Strong MATLAB/Simulink, C/C++, real-time systems, and FPGA I/O familiarity
Experience integrating HIL benches with production firmware and hardware prototypes
Proven ability to lead distributed teams and communicate with client engineering leadership
BS/MS in Electrical, Mechatronics or Controls Engineering
Nice to have: semiconductor capital equipment or EUV/DUV source exposure; Python test automation; SECS/GEM or EtherCAT; prior work in ITAR/EAR environment