Senior Design Verification Engineer Memory Controller Subsystem (HBM)

Calsoft Labs

San Jose, CA
30+ days ago

Highlights

Develop verification plans, UVM testbenches, test cases, assertions (SVA), and functional coverage. Execute regressions, debug RTL/design issues, and drive functional and code coverage closure.

Numbers & Facts

Location

San Jose, CA

Description

Experience: 5 12+ Years

Responsibilities

Verify the HBM-based Memory Controller subsystem using SystemVerilog/UVM.
Develop verification plans, UVM testbenches, test cases, assertions (SVA), and functional coverage.
Verify the HBM protocol, memory transactions, scheduling, ECC, QoS, power management, and performance.
Execute regressions, debug RTL/design issues, and drive functional and code coverage closure.
Collaborate with Architecture, RTL, and Validation teams through verification signoff.

Required Skills

Strong SystemVerilog/UVM expertise.
Experience verifying DDR/HBM memory controllers or memory subsystems.
Good understanding of HBM/DDR protocols, AXI interfaces, and memory architecture.
Experience with assertions, constrained-random verification, coverage closure, and VIP integration.
Proficiency with Xcelium/VCS/Questa and scripting (Python/Perl/Shell).