Design Verification Engineer, Principal

Design Verification Engineer, Principal
Santa Clara, CA - Onsite
Full Time

As a leading member of the Network Switching team you will develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers and contribute to the methodology behind such development. Your role may also include project management and leading a team of verification engineers on a project level.
Activities may include:
Writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete.
Developing tests and tuning the environment to achieve coverage goals. Debugging failures and working with designers to resolve issues.
Verifying boot code and architecting, developing, and maintaining tools to streamline the design of state-of-the-art multi-core SoCs.
Transforming the requirements from the engineering teams into software tools that are both easy to use and scalable within a highly parallel compute environment.
Unit and regression testing of software tools.

What We're Looking For
· BS Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of verification and firmware and software development experience (or MS/PhD with 5+ years experience).
· Proven track records of leading Design Verification implementation activity. Tape-out of complex SOC under tight schedule.
· In depth understanding and experience with System Verilog, UVM.
· In depth experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment.
· Experience with scripting language such as Python or Perl and EDA Verification tools.
· Experience with Object-Oriented Design and implementation.
· Good understanding of Linux O.S.
· Good programming skills desired, especially C++ and ARM assembly.
· Understanding of networking protocols, a plus.


Other Skills:
• Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision.
• Requires the ability to accept and work with differing opinions.
• Cannot be a close-minded developer.
• Must be able to learn on the fly and work in a fast-paced environment.

Recruiter Submission Template –

Full Name:
Degree (BS/MS/PhD) – Major, University & Completion Year:
Total Design Verification Experience (Years):
Total SoC Verification Experience (Years):
Experience leading Design Verification implementation and tape-out of complex SoCs (Yes/No – details):
SystemVerilog Experience (Years – details):
UVM Experience (Years – details):
Experience writing detailed Verification Test Plans (Yes/No – details):
Experience building Constrained Random Verification Environments (Yes/No – details):
Experience with Coverage-Driven Verification & Coverage Closure (Yes/No – details):
Experience with Python and/or Perl Scripting (Years – details):
Experience using EDA Verification Tools (Specify tools):
Experience with Object-Oriented Programming/Design (Yes/No – details):
Linux Experience (Years – details):
C++ Programming Experience (Years – details):
ARM Assembly Experience (Yes/No – details):
Experience with Multi-Core SoC Verification and Boot Code Verification (Yes/No – details):
Experience leading verification teams or project-level verification activities (Yes/No – details):
Understanding of Networking Protocols (Ethernet, TCP/IP, Switching, etc.) (Yes/No – details):
Motivation / Reason for interest in this position:
Contact Number:
Email ID:
LinkedIn Profile URL:
Full Address (Street, City, State, Zip Code):
Notice Period:
Current Work Authorization Status:
Expected Salary:
Are you able to relocate on your own expenses and work Santa Clara, CA - Onsite?