Design Verification Engineer

Responsibilities

Develop and maintain UVM-based verification environments Verify CPU subsystems and instruction execution Implement constrained-random testing Integrate Instruction Set Simulators ISS with DV environments Debug complex functional issues across hardware and testbench

Requirements

5 years Design Verification experience Strong skills in • SystemVerilog • UVM • Testbench architecture Experience verifying processor or CPU subsystems

Preferred

• Familiarity with Instruction Set Simulators Spike or similar • Experience with random instruction generators • Knowledge of processor software toolchains