p>RESPONSIBILITIES: • Work with the integrated circuit designers and chip leads to determine the chip floor plan; this includes strategies for power and ground distribution as well as working with packaging engineer to determine pad locations • Accurately estimate the schedule for the layout work and identify areas of complexity that need early investigation • Perform layout of custom RF and analog circuit blocks with attention to matching and minimizing parasitic capacitance in the layout • Perform design rule checking, electrical rule checking and layout versus schematic checks and resolve errors • Perform top-level layout integration with electrostatic discharge structures and pad assembly and perform final tape out (including density fill, running design for manufacturability checks and sharing GDS with the foundry) • Work with EDA suppliers to trial new tools and features • Generate guides and demos for others in the team to showcase improvements in layout technique.
PREferred SKILLS AND EXPERIENCE:
• Strong analog layout skills • Experience in advanced node IC layouts such as 22nm, 16nm, 7nm, 5nm or below • Experience in layout of circuits with frequencies up to 50GHz • Experience in layout of sensitive RF blocks such as low noise amplifiers, voltage controlled oscillators and mixers • Experience with skill programming • Experience with shell scripting, Perl, Python or similar language • Experience managing revision control systems • Understanding of layout considerations for device matching, coupling and noise isolation • Working knowledge of Linux • Excellent communication skills (both oral and written) are required • Able to work independently on challenging problems.