UNKNOWN

FEED

Develop and qualify ALD, CVD, and PECVD processes for gate dielectrics, high-k materials, inter-layer dielectrics (ILD), and spacer films at 2nm-class nodes. The facility houses logic, memory, packaging, test, and lithography mask production under one roof, optimized for rapid iteration and maximum compute density per square foot.

Tesla Inc

Sr. Process Engineer, Dielectric Deposition, Terafab

The facility houses logic, memory, packaging, test, and lithography mask production under one roof, optimized for rapid iteration and maximum compute density per square foot. You will develop and own etch processes across three distinct chip families: edge-inference processors, space-hardened chips for orbital satellites, and high-bandwidth memory.

Sr. Process Engineer, Dry Etch, Terafab

Develop and qualify electrochemical deposition (ECD) processes for copper damascene interconnect and through-silicon via (TSV) fill across all metal levels including metrology monitoring and defect inspection for bath health and process control. You'll control void-free fill, thickness uniformity, and grain structure while managing bath chemistry, current distribution, and seed layer interactions across extreme aspect ratios and feature sizes.

Sr. Process Engineer, Plating, Terafab

You will develop and own wet clean and etch processes across three distinct chip families: edge-inference processors, space-hardened chips for orbital satellites, and high-bandwidth memory. Develop and qualify post-etch and post-CMP wet clean processes including single-wafer spin clean, megasonic, and dilute chemical clean steps.

Sr. Process Engineer, Wet Etch, Terafab

The facility houses logic, memory, packaging, test, and lithography mask production under one roof, optimized for rapid iteration and maximum compute density per square foot. You will develop and own CMP processes across three distinct chip families: edge-inference processors, space-hardened chips for orbital satellites, and high-bandwidth memory.

Sr. Process Engineer, Chemical Mechanical Planarization, Terafab

OTHER

This job requires strong technical capability, a good understanding of server CPU technologies, and highly effective communication skills to debug systems-level issues from firmware level to applications level, working together as a team to resolve them to the satisfaction of our customers. This dynamic, highly visible role drives product Quality & Reliability related data analysis presenting to higher management internally, and external customers to improve customer satisfaction and build customer confidence.

Advanced Micro Devices, Inc

Product Quality & Reliability Engineer

[AW]-iCims

The facility houses logic, memory, packaging, test, and lithography mask production under one roof, optimized for rapid iteration and maximum compute density per square foot. Degree in Electrical Engineering, Chemical Engineering, Mechanical Engineering, Materials Science, Computer Science, Chemistry, Optics, Physics, Mathematics, or a related technical field, or equivalent experience.

Lithography Engineer, OPC, Terafab

Define furnace cleaning, fluxing, and metal-treatment practices that maximize melt quality, recover metal from dross, and extend refractory life, while leading adoption of new metal-cleaning concepts across the melt path. Own the design, definition, implementation, and long-term sustainment of Melt Center processes that deliver consistent, high-quality molten aluminum to Tesla's high-pressure die casting (HPDC) operations.

Sr. Foundry Process Engineer

Work hands-on on the fab floor - commission systems, measure reality against CAD, and debug the multi-variable failures that only surface at scale (tolerance stack-ups, thermal growth, dynamic loads). Work from first principles - evaluate trade-offs (why 5-point vs 3-point support?), select materials against thermal, mechanical, and cost constraints, and defend the design with physics rather than heuristics.

Sr. Mechanical Engineer, Terafab

You also need enough fluency in optical proximity correction, inverse lithography, source-mask optimization, mask process correction, and mask rule checks to co-specify processes that computational lithography can actually use, including curvilinear patterns and full-chip ILT - and that we can inspect, repair, and match to the scanner. 5+ years of hands-on photomask process engineering experience in a mask shop or semiconductor fab, especially supporting advanced logic, memory, or foundry reticle production.

Sr. Engineer, Mask, Terafab

The facility houses logic, memory, packaging, test, and lithography mask production under one roof, optimized for rapid iteration and maximum compute density per square foot. Our year-round program places the best students in positions where they will grow technically, professionally, and personally through their experience working closely with their Manager, Mentor, and team.

Internship, Process Engineer, Dry Etch, Terafab (Winter/Spring 2027)

You will develop and own wet clean and etch processes across three distinct chip families: edge-inference processors, space-hardened chips for orbital satellites, and high-bandwidth memory. The facility houses logic, memory, packaging, test, and lithography mask production under one roof, optimized for rapid iteration and maximum compute density per square foot.

Internship, Process Engineer, Wet Etch, Terafab (Winter/Spring 2027)

Akoustis is now operating as a wholly owned subsidiary of SpaceX, providing industry leading RF filters using patented XBAW technology to help drive the mission of making human life multi-planetary and connecting the world through Starlink. You will be responsible for developing and implementing RF test solutions, managing test workflows, and driving process improvements across wafer probe and final test operations.

Space Exploration Technologies Corp

Yield Engineer, RF Final Test Integration Starlink/Akoustis

Sr. Yield Engineer, RF Final Test Integration Starlink/Akoustis

Minimum Qualifications: PhD in Electronics, Chemistry, Physics, Material Science, or related field with 5+ years of work experience; or Masters of Science with 8+ years of work experience; or Bachelors of Science with 12+ years of work experience. Develop new or modified processes, define best known method process recipes, and partner with the hardware engineering to define chamber requirements and characterize hardware designs to meet customer performance requirements.

From smartphones and tablets to wearables and automobiles, it’s hard to go more than a few hours without using a semiconductor-enabled device. The semiconductor industry touches nearly every person on the planet, and chipmakers continue to advance the technology that powers it all.    
As a trusted partner to the world’s leading semiconductor companies, we welcome challenges and we deliver. That’s why, today, nearly every advanced chip is built with Lam technology.   
Our innovative wafer fabrication equipment and services allow chipmakers to build smaller and better performing devices. We combine superior systems engineering, technology leadership, and a strong values-based culture, with an unwavering commitment to our customers.

Lam Research Corp

Field Process Engineer 5

As such, our packaging engineers are involved with defining packaging equipment project requirements, estimating packaging equipment costs, creating packaging flow diagrams, providing onsite construction support, and start-up and commissioning of the packaging equipment. Packaging Engineers work closely with our process, controls, and building system engineers to scope, layout, install, and commission packaging equipment lines for our food and beverage industry clients.

External Dennis Group Jobs

Entry Level Packaging Systems Design Engineer I (Start Summer 2027)

This position requires the capability to closely work with power supply designs, mechanical and thermal teams, firmware development and validation teams, PCB layout engineers, and internal and external design stakeholders to create high-quality products and smooth volume production within a tight schedule. This includes the physical design of multilevel boards, DFM (Design for Manufacturing), power regulation, board bring-up qualification and debug, thermal, signal integrity, and EMI (Electro-Magnetic Interference).

Sr. Platform Hardware Design Engineer

Lead translation of beam path designs into physical optomechanical layouts, producing complete and accurate BOMs in close collaboration with Laser team leadership. Entrepreneurial mindset: thrives in a startup environment; self-directed and energized by building laser engineering capability from the ground up.

Focused Energy GmbH

Senior Laser Engineer

With 30,000 employees working together, Tetra Tech provides clear solutions to complex problems by Leading with Science to address the entire water cycle, protect and restore the environment, design sustainable and resilient infrastructure, and support the clean energy transition. Please note that Tetra Tech considers various factors in determining pay, including but not limited to: education, relevant and demonstrated work experience in the role, skills, geographic location, qualifications, certifications, and other competencies relevant to the needs of the business.

YEAR

Tetra Tech is a leading provider of consulting, engineering, and technical services worldwide. Our reputation rests on the technical expertise and dedication of our employees—16,000 people working together across disciplines and time zones to provide smart, sustainable solutions for challenging projects. We are proud to be home to leading technical experts in water, environment, infrastructure, resource management, energy, and international development. Tetra Tech combines the resources of a global, multibillion dollar company with local, client-focused delivery in 400 locations around the world. We offer competitive compensation and benefits and are searching for innovative people to join our teams.

Tetra Tech Inc

Electrical Engineer (Hybrid)

Note to staffing and direct hire agencies: In the event a recruiter or agency who is not on our preferred supplier list submits a resume/candidate to anyone in the company, AtkinsRéalis family of companies, we explicitly reserve the right to recruit and hire the candidate(s) at our discretion and without any financial obligation to the recruiter or agency. As an entry-level Full-Time employee, you will enjoy a robust rewards package including enrollment into Emerge, our new graduate experience, providing: Opportunities to work on various projects of ranging size and scope.

Packer Jobs in Arizona

Sr. Process Engineer, Dielectric Deposition, Terafab Tesla Inc

Sr. Process Engineer, Dry Etch, Terafab Tesla Inc

Sr. Process Engineer, Plating, Terafab Tesla Inc

Sr. Process Engineer, Wet Etch, Terafab Tesla Inc

Sr. Process Engineer, Chemical Mechanical Planarization, Terafab Tesla Inc

Product Quality & Reliability Engineer Advanced Micro Devices, Inc

Lithography Engineer, OPC, Terafab Tesla Inc

Sr. Foundry Process Engineer Tesla Inc

Sr. Mechanical Engineer, Terafab Tesla Inc

Sr. Engineer, Mask, Terafab Tesla Inc

Internship, Process Engineer, Dry Etch, Terafab (Winter/Spring 2027) Tesla Inc

Internship, Process Engineer, Wet Etch, Terafab (Winter/Spring 2027) Tesla Inc

Yield Engineer, RF Final Test Integration Starlink/Akoustis Space Exploration Technologies Corp

Sr. Yield Engineer, RF Final Test Integration Starlink/Akoustis Space Exploration Technologies Corp

Field Process Engineer 5 Lam Research Corp

Entry Level Packaging Systems Design Engineer I (Start Summer 2027) External Dennis Group Jobs

Sr. Platform Hardware Design Engineer Advanced Micro Devices, Inc

Senior Laser Engineer Focused Energy GmbH

Electrical Engineer (Hybrid) Tetra Tech Inc

Its/Traffic Engineer AtkinsRealis

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