1,756 Results for

Cad Engineer Jobs in San Francisco, CA

Jobs

New!

Alameda, CA1 day ago

$90,000–$110,000 Per Year

The role involves close collaboration with designers, engineers, project managers, and field teams to keep documents consistent, organized, and ready for the field while managing multiple projects to meet schedules and deadlines. Information collected and processed as part of your Jobot candidate profile, and any job applications, resumes, or other information you choose to submit is subject to Jobot's Privacy Policy, as well as the Jobot California Worker Privacy Notice and Jobot Notice Regarding Automated Employment Decision Tools which are available at jobot.com/legal.

New!

San Francisco, CA2 days ago

$100,000–$130,000 Per Year

Information collected and processed as part of your Jobot candidate profile, and any job applications, resumes, or other information you choose to submit is subject to Jobot's Privacy Policy, as well as the Jobot California Worker Privacy Notice and Jobot Notice Regarding Automated Employment Decision Tools which are available at jobot.com/legal. Completes project designs, drawings, specifications, system studies, calculations, correspondence, survey, code studies, and construction administration, as necessary.

New!

Mountain View, CA2 days ago

$200,000–$260,000 Per Year

Information collected and processed as part of your Jobot candidate profile, and any job applications, resumes, or other information you choose to submit is subject to Jobot's Privacy Policy, as well as the Jobot California Worker Privacy Notice and Jobot Notice Regarding Automated Employment Decision Tools which are available at jobot.com/legal. Founded by industry veterans from leading aerospace and satellite organizations, the company has rapidly grown into a team of over 200 engineers, scientists, and innovators focused on building next-generation space infrastructure.

New!

Hayward, CA2 days ago

New!

San Francisco, CA2 days ago

$115,000–$155,000 Per Year

Information collected and processed as part of your Jobot candidate profile, and any job applications, resumes, or other information you choose to submit is subject to Jobot's Privacy Policy, as well as the Jobot California Worker Privacy Notice and Jobot Notice Regarding Automated Employment Decision Tools which are available at jobot.com/legal. High Performance Buildings experience design; Mechanical/HVAC systems for Biotech, Labs, Healthcare, Science & Technology, Mission Critical, and Commercial facilities.

New!

SANTA CLARA, CA3 days ago

Full-time
Employee

Provides Risk Ratings in Agile on Arista components based on single/multi-sourcing, lifecycle, quality issues, and component availability for volume production. Performs component research by collaborating with designers, manufacturers, and supply chain to find components that meet performance, pricing, availability, and volume production needs.

New!

Benicia, CA5 days ago

We take our ‘focused on the future’ mantra seriously – whether we’re supporting lifesaving oxygen generation strategies for remote medical facilities, solving complex applications featuring industrial gases, providing mission critical technologies for our military, or engineering clean power solutions for land and sea. RIX Industries is a technology-focused company specializing in the design, development and manufacturing of gas generation systems, precision compressor solutions, and cryogenic cooling technologies for critical applications in Marine, Aerospace, Land, Energy, Industrial, Medical, and Critical Infrastructure markets.

Hayward, CA11 days ago

$100,000–$140,000 Per Year
Full-time

CONSIDERED EXPERIENCE INCLUDES: Machining Applications Engineer Manufacturing Engineering Process Engineer CNC Programming Machine Tools Methods Development Tooling Configuration Machine Shop Mills Lathes Machining Centers #DiedreMoire #JobSearch #JobHunt #JobOpening #Hiring #Job #Jobs #Careers #Employment #jobposting #CNCJobs #EngineeringJobs #ApplicationsEngineer. Activities: • Visit customer sites (Manufacturing Facilities) and review current manufacturing equipment and systems and anticipated designs and manufacturing challenges related to engine blocks, crank shafts, cam shafts, gear boxes, and similar power train components.

sunnyvale, CA30+ days ago

We design cutting edge consumer electronics products with highly complex surfaces and advanced engineering and we are looking for a talented CAD engineer to join us in designing, building, and executing our exciting roadmap of products. You will provide support in advanced CAD surfacing, developing novel CAD tools and processes, drawing support, and generally levelling up the CAD capability of the entire team.

San Jose, CA30+ days ago

$135,000–$165,000 Per Year

As an Astera Labs Physical Design/CAD Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity.

Santa Clara, CA30+ days ago

Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or equivalent professional experience in lieu of a formal degree. Collaboration and Support: Collaborate with cross-functional teams, including, foundry engineers, design engineers, layout designers, and software developers, to provide technical guidance, support, and training on CAD and EDA tools and methodologies.

San Jose, CA30+ days ago

$95,000–$150,000 Per Year

The ideal candidate will be responsible for supporting tools and infrastructures to help design semiconductor products using advanced CAD tools, while also providing support for EDA tools and automating workflows through scripting and DevOps practices. Pay and Location: Pay is based on market location and may vary based on factors including experience, skills, education and other job-related reasons.

Sunnyvale, CA7 days ago

From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. We"re the driving force behind Google"s groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future.

Sunnyvale, CA30+ days ago

In this role you will work with CI2 Silicon Development teams and your peers in the Infrastructure Tools and Methodology team to develop and enhance design tools and design flows that speed the development of CI2s ground-breaking TPU CPU and networking chips and enable them to provide generational improvements in performance power and cost while enhancing reliability. From software to hardware our teams are shaping the future of world-leading hyperscale computing with key teams working on the development of our TPUs Vertex AI for Google Cloud Google Global Networking Data Center operations systems research and much more.

Mountain View, CA30+ days ago

Applyshare linkCopy linkemailEmail a friendinfo_outlineXNote By applying to this position you will have an opportunity to share your preferred working location from the following San Diego CA USA Mountain View CA USA.Minimum qualificationsBachelors degree in Computer Engineering or a related field or equivalent practical experience.10 years of experience in VLSI design software development front-end CAD or EDA tool development. ResponsibilitiesDevelop front-end CAD tools and flows for Google Silicon SoC projects in various domains RTL generation design verification AI-enabled CAD flows designIP quality assurance and release management design spec management internal CAD tool development etc.

Mountain View, CA9 days ago

Develop front-end CAD tools and flows for Google Silicon SoC projects in various domains (RTL generation, design verification, AI-enabled CAD flows, design/IP quality assurance and release management, design spec management, internal CAD tool development, etc.). Experience with front-end design tools, such as lint, CDC/RDC, or simulation tools and HDL design languages and with front-end design development and integration process.

Santa Clara, CA30+ days ago

As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. In this role, you'll install and optimize PDKs, manage EDA tool flows, and partner with analog, digital, and software teams to continuously improve design efficiency.

San Jose, CA30+ days ago

The role involves working closely with design teams to ensure smooth tool and PDK integration for ongoing projects. Set up and maintain EDA tool environments, primarily Cadence tools (Virtuoso, Innovus, Tempus, etc.).

New!

Pleasanton, California3 days ago

Accsys Technologies, a division of HPES designs and manufactures ion RF LINAC systems (radio frequency linear accelerator), which are used in Particle Beam Therapy systems and R&D applications. We are seeking a detail-oriented CAD Engineer to support a high-priority initiative focused on improving and updating a large volume of existing engineering drawings.

Sunnyvale, CA30+ days ago

In this role, you will have the opportunity to directly influence the circuit design on various technology nodes and develop CAD flows for analog circuit SPICE simulation, netlist, design environment, and analyze waveforms, results data processing. In this highly visible role, your primary responsibilities will include: Solving issues related to transistor level simulations on Analog, RF and Microwave applications with Spice simulators on command-line and Virtuoso environment.

San Jose, CA30+ days ago

$127,100–$226,000 Per Year

This individual will be hands-on, heavily involved in day-to-day design/layout issues and in addition, interact with EDA vendors, the PDK development and process technology teams to provide timely solutions, and develop, maintain, and support utilities to improve productivity. Expertise in the following CAD Tools: Virtuoso Studio 25.1, Cadence Maestro, Spectre, Virtuoso Layout, Quantus QRC, Voltus-XFi/EMIR, EMX, and Synopsys Hspice, Primesim, StarRC, Quickcap, and Mentor Calibre/PERC.

Santa Clara, CA30+ days ago

Own and manage the release process for custom RAM circuit macros delivered to Place-and-Route (PNR) teams - including gatekeeping all collateral, coordinating with management on release schedules, and ensuring both internal and external customer teams are ready for each release. Ensure seamless integration of RAM compilers into PNR flows across NVIDIA - understand how compilers are used downstream, triage and resolve bugs related to RAM compiler builds.

New!

Newark, CA5 days ago

$115,000–$125,000 Per Year

Five or more years of experience with plastics design, Class A surfaces, front crash, aero features, lighting integration, module integration, tooling, resins, supply base, fit and finish, gap and flush, module concept, thermal expansion, structural design, paint (matching). We're ALTEN Technology USA, an engineering company helping clients bring groundbreaking ideas to life—from advancing space exploration and life-saving medical devices to building autonomous electric vehicles.

Headquarters, CA16 days ago

For candidates who receive an offer at the posted level, the starting base salary (for non-sales roles) or base salary + commission target (for sales/com-missioned roles) is expected to be the annual range listed below. Act as the definitive technical liaison to our external P&R ASIC vendor, compiling comprehensive design handoff packages and reviewing post-layout parasitic data to secure tape-out closure.

Santa Clara, CA30+ days ago

You would be responsible for supporting and maintaining CAD tools used by IC designers including Virtuoso, IC-Manage, DRC/LVS verification tools, extractions, and spice simulation tools. What we need to see: B.S. in Electrical Engineering or Computer Science (or equivalent experience); MS preferred 5+ years of work experience Basic understanding of mosfet device behavior, CMOS layout, and VLSI design.

Santa Clara, CA30+ days ago

Perform expert debug of design errors to direct expeditious resolution: explaining user errors to designers; explaining techfile errors to the foundry support team, and explaining tool errors to EDA partners. You would be responsible for supporting and maintaining CAD tools used by IC designers including Virtuoso, IC-Manage, DRC/LVS verification tools, extractions, and spice simulation tools.

santa clara, CA30+ days ago

Santa Clara, CA30+ days ago

Ability to collaborate across teams: Strong interpersonal, communication and teamwork skills, with a track record of working closely with hardware and design teams to facilitate EMIR signoff. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

Mountain View, CA30+ days ago

$119,800–$234,700 Per Year

There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year. Partner closely with Physical Design teams to: • Enable early PV runs • Debug complex DRC/LVS/ERC/PERC issues • Identify systemic design or flow gaps and drive fixes to closure.

San Francisco, CA30+ days ago

Today, Astranis satellites provide dedicated, secure networks to highly-sophisticated customers across the globe large enterprises, sovereign governments, and the US military. Astranis has raised over $750 million from some of the worlds best investors, from Andreessen Horowitz to Blackrock and Fidelity, and employs a team of 450 engineers and entrepreneurs.

San Francisco, CA30+ days ago

San Jose, CA30 days ago

$145,800–$194,400 Per Year

From enabling systems to make cities safer and more connected, to powering the data centers behind many of the worlds biggest companies and hyperscale cloud providers, to meeting the massive and ever-growing data storage needs of the AI era, WD is fueling a brighter, smarter future. An employees pay position within the salary range may be based on several factors including but not limited to (1) relevant education; qualifications; certifications; and experience; (2) skills, ability, knowledge of the job; (3) performance, contribution and results; (4) geographic location; (5) shift; (6) internal and external equity; and (7) business and organizational needs.

Palo Alto, CA30+ days ago

$120,000–$130,000 Per Year

Our application, software, and industry teams work directly with leading Fortune 500 companies-including Lockheed Martin, Mercedes-Benz, Boehringer Ingelheim, and Mitsubishi Chemical-to prepare quantum solutions for real-world impact. Actual compensation may vary outside of these ranges and is dependent on various factors including but not limited to a candidate's qualifications including relevant education and training, competencies, experience, geographic location, and business needs.

mountain view, CA30+ days ago

$120,000–$200,000 Per Year

The ASIC/SOC Physically Design CAD Engineer will be responsible for creating and maintaining our CAD flow and infrastructure to produce performant and functionally correct silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies in leading-edge process nodes. MatX's mission is to make the world's best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability.

San Jose, CA30+ days ago

Strong hands-on experience with Cadence Virtuoso custom design environment Deep understanding of custom layout and verification flows Proficiency in SKILL, Perl, Python, and TCL scripting Experience with PDK enablement, libraries, and advanced nodes Knowledge of Virtuoso-Innovus handoff flows Familiarity with JIRA, GitHub, and Perforce Good to Have: Signal Integrity / Power Integrity (SIPI) experience. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry.

New!

Emeryville, CA5 days ago

$210,000–$260,000 Per Year

Furthermore, this digital platform is fully programmable in the way 3D printing is digital—but whereas 3D printing produces parts of a single material using a single process, the Matter Compiler technology platform is a multi-process, multi-material system: bits and raw materials go in, and complete, functional micromachines come out. About The Role: As a CAD Automation Engineer, you will have the opportunity to lead, innovate, and shape our CAD/automation workflows by developing generative and programmatic CAD pipelines that transform design specifications into manufacturable micro-device assemblies.

Santa Clara, CA30+ days ago

Responsibilities include user support for Behavioral, RTL and Analog Designs, Schematics, Analog Mixed-Signal Simulations, IC Physical Design layout, CAD tool customizations, Linux Support, implementation and testing of new software tools and deploy new CAD Tool flows. The Principal CAD Engineer will also interface with EDA Tool Vendors and have responsibilities for implementation and performance testing of new software releases, prior to deploying to IC Designers across multiple engineering sites.

Santa Clara, CA30+ days ago

Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. As a key CAD member of Marvell Central Engineering, you will play a leading role in developing next-generation Multi-die and Power Methodology, plus CAD flow automation and tool support.

Santa Clara, CA30+ days ago

The team works at the intersection of EDA tools, semiconductor process technology, and circuit design, partnering closely with: • Analog and mixed-signal IC design teams • Silicon photonics engineers • Foundry partners • EDA vendors • Device modeling and TCAD specialists. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones.

Santa Clara, CA30+ days ago

$110,000–$145,000 Per Year

Position Overview:Support and enhance the Analog CAD design flow across the full custom IC design cycle, including schematic, layout, simulation, and physical verification using Cadence Virtuoso and Calibre tools. Responsibilities:Support and optimize Analog CAD flows on the Cadence Virtuoso platform (Schematic, Layout, ADE).

San Jose30+ days ago

$181,100–$318,400 Per Year

DescriptionAs a member of our STA CAD team, you will: • Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs • Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure • Facilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency/productivity and silicon timing correlation • Develop and maintain scripts and methods for timing analysis and power reduction • Develop and support methodologies, tools, and flows used in the verification of timing constraints, drive best practices across design teams • Analysis of timing paths to identify key issues, including post-silicon timing debug • Work closely with EDA vendors to develop and incorporate new capabilities to solve technical problemsMinimum QualificationsMinimum requirement of BS and 10 years of relevant industry experience. Preferred QualificationsExpert power user of static timing analysis tools and flowsAdvanced programming skills with Python and Tcl or other high level programming languagesProven track record of development and deployment of complex CAD flows and automationFamiliar with STA of large high-performance SoC designs in deep sub-micron technologiesDeep understanding of noise, cross-talk, variation, margins, and timing modelsKnowledge of timing/SDC constraints, hands on experience in creation and validation of constraintsExcellent communicator who can accurately assess and describe issues to management as well as follow solutions through to completionPay & BenefitsAt Apple, base pay is one part of our total compensation package and is determined within a range.

Sunnyvale, CA19 days ago

Full-time
Employee

In this role, you will work with CI2 Silicon Development teams and your peers in the Infrastructure, Tools, and Methodology team to develop and enhance design tools and design flows that speed the development of CI2's ground-breaking TPU, CPU, and networking chips and enable them to provide generational improvements in performance, power, and cost while enhancing reliability. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Santa Clara, CA30+ days ago

We have some of the most forward-thinking and hardworking people in the world working with us and our product lines are growing fast in some of the hottest state of the art fields such as Artificial Intelligence, Deep Learning, Autonomous Vehicles, and Robotics. Proven history of delivering EDA / ECAD around Cadence System Capture and SPB Allegro Layout to aid system designers in sophisticated implementations.

Fremont, California30+ days ago

The VELO3D award-winning solution includes an integrated offering of hardware and software: Sapphire® metal AM production printer, Flow print preparation software, Assure quality assurance and control system, and an integrated manufacturing process that runs throughout the printing operation. Position Overview:As Senior Applications Engineer you will work directly with external customers and engineering groups within Velo3D to develop innovative and novel projects for additively manufactured production hardware.

Santa Clara, CA8 days ago

The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits. What you'll be doing: Work within a multi-functional team on various projects involving Pre-silicon and Post Silicon hardware design and related data.

Palo Alto, CA30+ days ago

$128,000–$312,000 Per Year

By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. Tesla's AI Hardware Team is looking for experienced, highly skilled VLSI engineers who enjoy working across the logic, circuit, methodology, and physical design levels.

Mountain View, CA9 days ago

You will be developing automated front-end CAD flows, managing complex EDA tool collaterals, and collaborating with cross-functional teams to resolve technical integration bottlenecks. Develop and maintain Front-End CAD flows and Electronic Design Automation (EDA) tool collaterals to optimize design productivity.

Sunnyvale, CA30+ days ago

Your work will involve modeling complex package and interposer structures, enabling high-accuracy extraction of S-parameters, and ensuring robust signal integrity, coupling, and shielding performance across advanced packaging and 3DIC systems. • Support and collaborate with design groups (Physical-design and integration, Circuit-design / Power / Package & System / Technology) on their Electromagnetics requirements for various post layout flows.

emeryville, CA30+ days ago

Furthermore, this digital platform is fully programmable in the way 3D printing is digital\u2014but whereas 3D printing produces parts of a single material using a single process, the Matter Compiler technology platform is a multi-process, multi-material system: bits and raw materials go in, and complete, functional micromachines come out. About The Role: As a CAD Automation Engineer, you will have the opportunity to lead, innovate, and shape our CAD/automation workflows by developing generative and programmatic CAD pipelines that transform design specifications into manufacturable micro-device assemblies.

Mountain View, CA30+ days ago

This role is to build a text-and-image-to-CAD system that turns natural language and sketches into editable, parametric 3D geometry with manufacturing constraints built in - starting with consumer product design. The process typically includes a Builder Event or equivalent working conversation, then a 48-hour Builder Challenge, then panel review with AI Fund build leadership.

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Cad Engineer Jobs in San Francisco, CA

Senior CAD Drafter/BIM Modeler Jobot

Plumbing Design Engineer Jobot

Principal Mechanical Engineer Jobot

Mechanical HVAC Controls/BAS Engineer Davron LLC

Mechanical Design Engineer Jobot

Electromechanical Component Engineer InESS Solutions Inc

Manufacturing Test Engineer RIX INDUSTRIES

Machine Tool Process Development Engineer - Hayward, CA Diedre Moire Corp.

Sr. CAD Engineer - Apple Vision Pro Apple Inc

Physical Design/CAD Engineer Astera Labs Inc

Senior Staff Physical Verification CAD engineer Marvell Technology Inc

Sr. CAD Engineer Monolithic Power Systems Inc

Senior Design Verification CAD Engineer, Silicon, Google Cloud Google LLC

Silicon CAD Engineer, University Graduate, PhD Google LLC

Staff Front-end CAD Engineer, Silicon Google LLC

Staff Front-End CAD Engineer, Silicon Google LLC

PDK/CAD Engineer Tenstorrent Inc

CAD Engineer (PDK & Cadence Customization) ACL Digital

CAD Engineer Hitachi

Analog Simulation/Env Automation CAD Engineer Apple Inc

IC CAD Engineer Broadcom Inc

Senior VLSI CAD Engineer NVIDIA Corp

CAD Engineer, Exterior Trim ALTEN Technology USA

Senior ASIC CAD Engineer Palo Alto Networks Inc

Senior Calibre CAD Engineer NVIDIA Corp

CAD Engineer NVIDIA Corp

Senior ICV CAD Engineer NVIDIA Corp

Senior Power Integrity Methodology CAD Engineer NVIDIA Corp

Senior Physical Verification CAD Engineer Microsoft Corp

CAD Engineer/Librarian Intern Fall 2026 Astranis Space Technologies Corp

CAD Engineer/Librarian Associate Fall 2026 Astranis Space Technologies Corp

EDA- CAD Engineer Western Digital Corp

Senior EDA/CAD Engineer PsiQuantum Corp

ASIC/SOC CAD Engineer MatX Inc

Staff Virtuoso Custom Layout CAD Engineer Lattice Semiconductor Corp

AI CAD Engineer Atomic Machines

Principal Engineer, CAD SiTime Corp

Senior Staff CAD Engineer, Multi-die 3DIC & Power Marvell Technology Inc

Principal Analog/Mixed Signal CAD Engineer Marvell Technology Inc

Analog CAD Engineer Omnivision Technologies

CAD Engineer - Timing for Gate-Level Flows & Methodologies Apple Inc

Silicon CAD Engineer, University Graduate, PhD Google

Senior CAD Engineer NVIDIA Corp

SolidWorks CAD Engineer (Applications Engineer) Velo3D

Software Engineer, CAD Automation NVIDIA Corp

Staff CAD Flow Engineer, Physical Implementation & Sign Off, AI Hardware Tesla Inc

Front-End CAD and IP Management Engineer, Silicon Google LLC

CAD Electromagnetic RFIC Simulation Engineer Apple Inc

Staff CAD Automation Engineer Atomic Machines Inc

Visiting Engineer: CAD Design AI Landing AI

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